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cy7c63722c cy7c63723c cy7c63743c encore? usb combination low-speed usb and ps/2 peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08022 rev. *e revised april 15, 2011 features encore? usb - enhanced component reduction ? internal oscillator eliminates the need for an external crystal or resonator ? interface can auto-configure to operate as ps/2 or usb with- out the need for external components to switch between modes (no general purpose i/o [gpio] pins needed to man- age dual mode capability) ? internal 3.3v regulator for usb pull-up resistor ? configurable gpio for real-world interface without external components flexible, cost-effective solution for applications that combine ps/2 and low-speed usb, such as mice, gamepads, joysticks, and many others. usb specification compliance ? conforms to usb specification, version 2.0 ? conforms to usb hid spec ification, version 1.1 ? supports one low-speed usb device address and three data endpoints ? integrated usb transceiver ? 3.3v regulated output for usb pull-up resistor 8-bit risc microcontroller ? harvard architecture ? 6-mhz external ceramic resonator or internal clock mode ? 12-mhz internal cpu clock ? internal memory ? 256 bytes of ram ? 8 kbytes of eprom ? interface can auto-configure to operate as ps/2 or usb ? no external components for switching between ps/2 and usb modes ? no gpio pins needed to manage dual mode capability i/o ports ? up to 16 versatile gpio pins, individually configurable ? high current drive on any gpio pin: 50 ma/pin current sink ? each gpio pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional cmos outputs ? maskable interrupts on all i/o pins spi serial communication block ? master or slave operation ? 2 mbit/s transfers four 8-bit input capture registers ? two registers each for two input pins ? capture timer setting with five prescaler settings ? separate registers for rising and falling edge capture ? simplifies interface to rf inputs for wireless applications internal low-power wake-up timer during suspend mode ? periodic wake-up with no external components optional 6-mhz internal oscillator mode ? allows fast start-up from suspend mode watchdog reset (wdr) low-voltage reset at 3.75v internal brown-out reset for suspend mode improved output drivers to reduce emi operating voltage from 4.0v to 5.5vdc operating temperature from 0c to 70c cy7c63723c available in 18-pin soic, 18-pin pdip cy7c63743c available in 24-pin soic, 24-pin pdip, 24-pin qsop cy7c63722c available in die form industry standard programmer support [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 2 of 53 logic block diagram functional overview encore usb?the new usb standard cypress has reinvented its leadership position in the low-speed usb market with a new family of innovative microcontrollers. introducing...encore usb??enhanced component reduction.? cypress has leveraged its design expertise in usb solutions to create a new family of low-speed usb microcontrollers that enables peripheral developers to design new products with a minimum number of components. at the heart of the encore usb te chnology is the breakthrough design of a crystalless oscillator. by integrating the oscillator into our chip, an external crystal or resonator is no longer needed. we have also integrated other external components commonly found in low-speed usb applications such as pull-up resistors, wake-up circuitry, and a 3.3v regulator. all of this adds up to a lower system cost. the cy7c637xxc is an 8-bit risc one-time-programmable (otp) microcontroller. the instruction set has been optimized specifically for usb and ps/2 operations, although the microcon- trollers can be used for a variety of other embedded applications. the cy7c637xxc features up to 16 gpio pins to support usb, ps/2 and other applications. the i/o pins are grouped into two ports (port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional cmos outputs with programmable drive strength of up to 50 ma output drive. additionally, each i/o pin can be used to generate a gpio interrupt to the microcontroller. note the gpio interrupts all share the same ?gpio? interrupt vector. the cy7c637xxc microcontrollers feature an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (6 mhz 1.5%). optionally, an external 6-mhz ceramic resonator can be used to provide a higher precision reference for usb operation. this clock generator reduces the clock-related noise emissions (emi). the clock generator prov ides the 6- and 12-mhz clocks that remain internal to the microcontroller. the cy7c637xxc has 8 kbytes of eprom and 256 bytes of data ram for stack space, user variables, and usb fifos. these parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. the low-voltage reset (lvr) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instruct ions at eprom address 0x0000. lvr will also reset the part when v cc drops below the operating voltage range. the watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. the microcontroller supports 10 maskable interrupts in the vectored interrupt controller. interrupt sources include the usb bus-reset, the 128- ? s and 1.024-ms outputs from the free-running timer, three usb endpoints, two capture timers, an internal wake-up timer and the gpio ports. the timers bits cause periodic interrupts when enabled. the usb endpoints interrupt after usb transactions complete on the bus. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge event. the gpio ports have a level of masking to select which gpio inputs ca n cause a gpio interrupt. for additional flexibility, the input transition polarity that causes an interrupt is programmable for each gpio pin. the interrupt polarity can be either rising or falling edge. the free-running 12-bit timer clocked at 1 mhz provides two interrupt sources as noted above (128 ? s and 1.024 ms). the timer can be used to measure the duration of an event under firmware control by reading the ti mer at the start and end of an wake-up 12-bit timer usb & d+,d? p1.0?p1.7 interrupt controller port 0 p0.0?p0.7 gpio 8-bit risc xtal ram 256 byte eprom 8k byte core brown-out reset xcvr watch timer dog 3.3v port 1 gpio capture timers usb engine ps/2 internal oscillator oscillator low reset voltage regulator timer spi xtalout xtalin/p2.1 vreg/p2.0 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 3 of 53 event, and subtracting the two va lues. the four capture timers save a programmable 8 bit range of the free-running timer when a gpio edge occurs on the two capture pins (p0.0, p0.1). the cy7c637xxc includes an integrated usb serial interface engine (sie) that supports the integrated peripherals. the hardware supports one usb device address with three endpoints. the sie allows the u sb host to communicate with the function integrated into the micr ocontroller. a 3.3v regulated output pin provides a pull-up sour ce for the external usb resistor on the d? pin. the usb d+ and d? usb pins can alternately be used as ps/2 sclk and sdata signals, so that products can be designed to respond to either usb or ps/2 modes of operation. ps/2 operation is supported with inte rnal pull-up resistors on sclk and sdata, the ability to disable the regulator output pin, and an interrupt to signal the start of ps/2 activity. no external compo- nents are necessary for dual usb and ps/2 systems, and no gpio pins need to be dedicated to switching between modes. slow edge rates operate in both modes to reduce emi. pin configurations 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 p0.0 p0.1 p0.2 p0.3 p1.0 p1.2 vss vreg/p2.0 p0.6 p1.5 p1.1 p1.3 d+/sclk p1.7 d?/sdata vcc 14 p0.7 10 vpp xtalin/p2.1 xtalout 12 13 7 8 p1.4 p1.6 24 23 p0.4 p0.5 24-pin soic/pdip/qsop cy7c63743c 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 p0.0 p0.1 p0.2 p0.3 vss vreg/p2.0 p0.4 p0.6 p0.7 d+/sclk d?/sdata vcc 18-pin soic/pdip p0.5 9 vpp xtalin/p2.1 xtalout cy7c63723c 5 14 p1.0 p1.1 top view 4 5 6 7 8 9 3 p0.2 1 p0.0 2 p0.1 25 p0.4 24 p0.5 23 p0.6 22 21 20 19 18 11 12 13 14 15 16 17 p0.3 p1.0 p1.2 p1.4 p1.6 vss vss vpp xtalin/p2.1 vreg xtalout vcc d-/sdata d+/sclk p0.7 p1.1 p1.3 p1.5 p1.7 cy7c63722c-xc die 10 pin definitions name i/o cy7c63723c cy7c63743c cy7c63722c description 18-pin 24-pin 25-pad d?/sdata, d+/sclk i/o 12 13 15 16 16 17 usb differential data lines (d? and d+), or ps/2 clock and data signals (sdata and sclk) p0[7:0] i/o 1, 2, 3, 4, 15, 16, 17, 18 1, 2, 3, 4, 21, 22, 23, 24 1, 2, 3, 4, 22, 23, 24, 25 gpio port 0 capable of sinking up to 50 ma/pin, or sinking controlled low or high programmable current. can also source 2 ma current, provide a resistive pull-up, or serve as a high-impedance input. p0.0 and p0.1 provide inputs to capture timers a and b, respec- tively. p1[7:0] i/o 5, 14 5, 6, 7, 8, 17, 18, 19, 20 5, 6, 7, 8, 18, 19, 20, 21 io port 1 capable of sinking up to 50 ma/pin, or sinking controlled low or high programmable current. can also source 2 ma current, provide a resistive pull-up, or serve as a high-impedance input. xtalin/p2.1 in 9 12 13 6-mhz ceramic resonator or external clock input, or p2.1 input xtalout out 10 13 14 6-mhz ceramic resonator return pin or internal oscillator output v pp 7 10 11 programming voltage supply, ground for normal operation v cc 11 14 15 voltage supply vreg/p2.0 8 11 12 voltage supply for 1.3-k ? usb pull-up resistor (3.3v nominal). also serves as p2.0 input. v ss 6 9 9, 10 ground [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 4 of 53 programming model refer to the cyasm assembler user?s guide for more details on firmware operation with the cy7c637xxc microcontrollers. program counter (pc) the 14-bit program counter (pc) allows access for up to 8 kbytes of eprom using the cy7c637xxc architecture. the program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. this instruction is typically a jump instruction to a reset handler that initializes the application. the lower 8 bits of the program counter are incremented as instructions are loaded and execut ed. the upper six bits of the program counter are incremented by executing an xpage instruction. as a result, the la st instruction executed within a 256-byte ?page? of sequential code should be an xpage instruction. the assembler directive ?xpageon? will cause the assembler to insert xpage in structions auto matically. as instructions can be either one or two bytes long, the assembler may occasionally need to insert a nop followed by an xpage for correct execution. the program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a call instruction. the program counter, carry flag, and zero flag are restored from the program stack only during a reti instruction. please note the program counter cannot be accessed directly by the firmware. the program stack can be examined by reading sram from location 0x00 and up. 8-bit accumulator (a) the accumulator is the general-purpose, do everything register in the architecture where results are usually calculated. 8-bit index register (x) the index register ?x? is availa ble to the firmware as an auxiliary accumulator. the x register also allows the processor to perform indexed operations by loading an index value into x. 8-bit program stack pointer (psp) during a reset, the program stack pointer (psp) is set to zero. this means the program ?stack? starts at ram address 0x00 and ?grows? upward from there. note that the program stack pointer is directly addressable under fi rmware control, using the mov psp,a instruction. the psp supports interrupt service under hardware control and call, ret, and reti instructions under firmware control. during an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. the first byte is stored in the memory addressed by the program stack pointer, then the psp is incre- mented. the second byte is stored in memory addressed by the program stack pointer and the psp is incremented again. the net effect is to store the pr ogram counter and flags on the program ?stack? and increment the program stack pointer by two. the return from interrupt (reti) instruction decrements the program stack pointer, then re stores the se cond byte from memory addressed by the psp. the program stack pointer is decremented again and the first by te is restored from memory addressed by the psp. after the program counter and flags have been restored from stack, the interrupts are enabled. the effect is to restore the program count er and flags from the program stack, decrement the program stack pointer by two, and reenable interrupts. the call subroutine (call) in struction stores the program counter and flags on the program stack and increments the psp by two. the return from subroutine (ret) instruction restores the program counter, but not the flags, from program stack and decrements the psp by two. note that there are restricti ons in using the jmp, call, and index instructions across the 4-kbyte boundary of the program memory. refer to the cyasm assembler user?s guide for a detailed description. 8-bit data stack pointer (dsp) the data stack pointer (dsp) supports push and pop instruc- tions that use the data stack for temporary storage. a push instruction will pre-de crement the dsp, then write data to the memory location addressed by the dsp. a pop instruction will read data from the memory loca tion addressed by the dsp, then post-increment the dsp. during a reset, the data stack pointer will be set to zero. a push instruction when dsp equals zero will write data at the top of the data ram (address 0xff). this would write data to the memory area reserved for a fifo for usb endpoint 0. in non-usb appli- cations, this works fine and is not a problem. for usb applications, the firmware should set the dsp to an appropriate location to avoid a memory conflict with ram dedicated to usb fifos. the me mory requirements for the usb endpoints are shown in section . for example, assembly instruc- tions to set the dsp to 20h (giving 32 bytes for program and data stack combined) are shown below. mov a,20h ; move 20 hex into accumulator (must be d8h or less to avoid usb fifos) swap a,dsp ; swap accumulato r value into dsp register address modes the cy7c637xxc microcontrollers support three addressing modes for instructions that requ ire data operands: data, direct, and indexed. data the ?data? address mode refers to a data operand that is actually a constant encoded in the instruct ion. as an example, consider the instruction that loads a with the constant 0x30: mov a, 30h this instruction will require two bytes of code where the first byte identifies the ?mov a? instruction with a data operand as the second byte. the second byte of the instruction will be the constant ?0xe8h?. a constant may be referred to by name if a prior ?equ? statement assigns th e constant value to the name. for example, the following code is equivalent to the example shown above. dspinit: equ 30h [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 5 of 53 mov a,dspinit direct ?direct? address mode is used when the data operand is a variable stored in sram. in that case, the one byte address of the variable is encoded in t he instruction. as an example, consider an instruction that loads a with the contents of memory address location 0x10h: mov a, [10h] in normal usage, variable names are assigned to variable addresses using ?equ? statements to improve the readability of the assembler source code. as an example, the following code is equivalent to the example shown above. buttons: equ 10h mov a, [buttons] indexed ?indexed? address mode allows the firmware to manipulate arrays of data stored in sram. the address of the data operand is the sum of a constant encoded in the instruction and the contents of the ?x? register. in normal usage, the constant will be the ?base? address of an array of data and the x register will contain an index that indicates which element of the array is actually addressed. array: equ 10h mov x,3 mov a, [x+array] this would have the effect of loading a with the fourth element of the sram ?array? that begins at address 0x10h. the fourth element would be at address 0x13h. instruction set summary refer to the cyasm assembler user?s guide for detailed infor- mation on these instructions. note that conditional jump instruc- tions (i.e., jc, jnc, jz, jnz) take five cycles if jump is taken, four cycles if no jump. mnemonic operand opcode cycles mnemonic operand opcode cycles halt 00 7 nop 20 4 add a,expr data 01 4 inc a acc 21 4 add a,[expr] direct 02 6 inc x x 22 4 add a,[x+expr] index 03 7 inc [expr] direct 23 7 adc a,expr data 04 4 inc [x+expr] index 24 8 adc a,[expr] direct 05 6 dec a acc 25 4 adc a,[x+expr] index 06 7 dec x x 26 4 sub a,expr data 07 4 dec [expr] direct 27 7 sub a,[expr] direct 08 6 dec [x+expr] index 28 8 sub a,[x+expr] index 09 7 iord expr address 29 5 sbb a,expr data 0a 4 iowr expr address 2a 5 sbb a,[expr] direct 0b 6 pop a 2b 4 sbb a,[x+expr] index 0c 7 pop x 2c 4 or a,expr data 0d 4 push a 2d 5 or a,[expr] direct 0e 6 push x 2e 5 or a,[x+expr] index 0f 7 swap a,x 2f 5 and a,expr data 10 4 swap a,dsp 30 5 and a,[expr] direct 11 6 mov [expr],a direct 31 5 and a,[x+expr] index 12 7 mov [x+expr],a index 32 6 xor a,expr data 13 4 or [expr],a direct 33 7 xor a,[expr] direct 14 6 or [x+expr],a index 34 8 xor a,[x+expr] index 15 7 and [expr],a direct 35 7 cmp a,expr data 16 5 and [x+expr],a index 36 8 cmp a,[expr] direct 17 7 xor [expr],a direct 37 7 cmp a,[x+expr] index 18 8 xor [x+expr],a index 38 8 mov a,expr data 19 4 iowx [x+expr] index 39 6 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 6 of 53 mov a,[expr] direct 1a 5 cpl 3a 4 mov a,[x+expr] index 1b 6 asl 3b 4 mov x,expr data 1c 4 asr 3c 4 mov x,[expr] direct 1d 5 rlc 3d 4 reserved 1e rrc 3e 4 xpage 1f 4 ret 3f 8 mov a,x 40 4 di 70 4 mov x,a 41 4 ei 72 4 mov psp,a 60 4 reti 73 8 call addr 50 - 5f 10 jmp addr 80-8f 5 jc addr c0-cf 5 (or 4) call addr 90-9f 10 jnc addr d0-df 5 (or 4) jz addr a0-af 5 (or 4) jacc addr e0-ef 7 jnz addr b0-bf 5 (or 4) index addr f0-ff 14 mnemonic operand opcode cycles mnemonic operand opcode cycles [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 7 of 53 memory organization program memory organization [1] after reset address 14 -bit pc 0x0000 program execution begins here after a reset 0x0002 usb bus reset interrupt vector 0x0004 128- ? s timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 usb endpoint 0 interrupt vector 0x000a usb endpoint 1 interrupt vector 0x000c usb endpoint 2 interrupt vector 0x000e spi interrupt vector 0x0010 capture timer a interrupt vector 0x0012 capture timer b interrupt vector 0x0014 gpio interrupt vector 0x0016 wake-up interrupt vector 0x0018 program memory begins here 0x1fdf 8 kb prom ends here (8k - 32 bytes). see note below figure 1. program memory space with interrupt vector table note 1. the upper 32 bytes of the 8k prom are reserved. theref ore, the user?s program must not overwrite this space. [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 8 of 53 data memory organization the cy7c637xxc microcontrollers provide 256 by tes of data ram. in normal usage, the sram is partitioned into four areas: progra m stack, data stack, user variables and usb endpoint fifos as shown below. figure 2. data memory organization i/o register summary i/o registers are accessed via th e i/o read (iord) and i/o write (iowr, iowx) instructions. iord reads the selected port into the accumulator. iowr writes da ta from the accumulator to the selected port. indexed i/o write (iowx) adds the contents of x to the address in the instruction to form the port address and writes data from the accumulator to the specified port. note that specifying address 0 with iowx (e .g., iowx 0h) means the i/o port is selected solely by the contents of x. note: all bits of all regi sters are cleared to all zeros on reset, except the processor status and control register ( figure 33 ). all registers not listed are reserved, and should never be written by firmware. all bits marked as re served should always be written as 0 and be treated as undefined by reads. after reset address 8-bit dsp 8-bit psp 0x00 program stack growth (user?s firmware moves dsp) 8-bit dsp user selected data stack growth user variables 0xe8 usb fifo for address a endpoint 2 0xf0 usb fifo for address a endpoint 1 0xf8 usb fifo for address a endpoint 0 top of ram memory 0xff table 1. i/o register summary register name i/o address read/write function fig port 0 data 0x00 r/w gpio port 0 7 port 1 data 0x01 r/w gpio port 1 8 port 2 data 0x02 r auxiliary input register for d+, d?, vreg, xtalin port 0 interrupt enable 0x04 w interru pt enable for pins in port 0 37 port 1 interrupt enable 0x05 w interru pt enable for pins in port 1 38 port 0 interrupt polarity 0x06 w interru pt polarity for pins in port 0 39 port 1 interrupt polarity 0x07 w inter rupt polarity for pins in port 1 port 0 mode0 0x0a w controls output configuration for port 0 9 port 0 mode1 0x0b w port 1 mode0 0x0c w controls output configuration for port 1 11 port 1 mode1 0x0d w 12 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 9 of 53 usb device address 0x10 r/w u sb device address register 15 ep0 counter register 0x11 r/w usb endpoint 0 counter register 18 ep0 mode register 0x12 r/w usb endpoi nt 0 configuration register 16 ep1 counter register 0x13 r/w usb endpoint 1 counter register 18 ep1 mode register 0x14 r/w usb end point 1 configuration register ep2 counter register 0x15 r/w usb endpoint 2 counter register 18 ep2 mode register 0x16 r/w usb end point 2 configuration register usb status & control 0x1f r/w usb status and control register 14 global interrupt enable 0x20 r/w global interrupt enable register endpoint interrupt enable 0x21 r/w usb endpoint interrupt enables timer (lsb) 0x24 r lower 8 bits of free-running timer (1 mhz) 24 timer (msb) 0x25 r upper 4 bits of free-running timer 25 wdr clear 0x26 w watchdog reset clear - capture timer a rising 0x40 r rising edge capture timer a data register capture timer a falling 0x41 r falling edge capture timer a data register capture timer b rising 0x42 r rising edge capture timer b data register 29 capture timer b falling 0x43 r falling edge capture timer b data register 30 capture timer configuration 0x44 r/w capture timer configuration register 32 capture timer status 0x45 r capture timer status register 31 spi data 0x60 r/w spi read and write data register 21 spi control 0x61 r/w spi status and control register 22 clock configuration 0xf8 r/w internal / external clock configuration register processor status & control 0xff r/w processor status and control 33 table 1. i/o register summary (continued) register name i/o address read/write function fig [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 10 of 53 clocking the chip can be clocked from either the internal on-chip clock, or from an oscillator based on an external resonator/crystal, a s shown in figure . no additional capacitance is included on chip at the xtal in/out pins. operation is cont rolled by the clock configuration register, figure . figure 3. clock oscillator on-chip circuit figure 4. clock configuration register (address 0xf8) bit 7: ext. clock resume delay external clock resume delay bi t selects the delay time when switching to the external oscillator from the internal oscillator mode, or when waking from suspend mode with the external oscillator enabled. 1 = 4 ms delay. 0 = 128 ? s delay. the delay gives the oscillator time to start up. the shorter time is adequate for operation with ceramic resonators, while the longer time is preferred for start-up with a crystal. (these times do not include an initial oscillator start-up time which depends on the resonating element. this time is typically 50?100 ? s for ceramic resonators and 1?10 ms for crystals). note that this bit only selects the delay time for the external clock mode. when waking from suspend mode with the inter- nal oscillator (bit 0 is low), the delay time is only 8 ? s in addition to a delay of approximately 1 ? s for the oscillator to start. bit [6:4]: wake-up timer adjust bit [2:0] the wake-up timer adjust bits are used to adjust the wake-up timer period. if the wake-up interrupt is enabled in the global interrupt en- able register, the microcontroller will generate wake-up inter- rupts periodically. the frequency of these periodical wake-up interrupts is adjusted by setting the wake-up timer adjust bit [2:0], as described in section . one common use of the wake-up interrupts is to generate periodical wake-up events during suspend mode to check for changes, such as looking for movement in a mouse, while maintaining a low average power. bit # 76543210 bit name ext. clock resume delay wake-up timer adjust bit [2:0] low-voltage reset disable precision usb clocking enable internal clock output disable external oscillator enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 xtalout xtalin clk2x (12 mhz) clock doubler clk1x (6 mhz) (to microcontroller) (to usb sie) port 2.1 internal osc int clk output disable ext clk enable [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 11 of 53 bit 3: low-voltage reset disable when v cc drops below v lvr (see section for the value of v lvr ) and the low-voltage reset circuit is enabled, the micro- controller enters a partial suspend state for a period of t start (see section for the value of t start ). program execution be- gins from address 0x0000 after this t start delay period. this provides time for v cc to stabilize before the part executes code. see section for more details. 1 = disables the lvr circuit. 0 = enables the lvr circuit. bit 2: precision us b clocking enable the precision usb clocking enable only affects operation in internal oscillator mode. in that mode, this bit must be set to 1 to cause the internal clock to automatically precisely tune to usb timing requ irements (6 mhz 1.5%) . the fre- quency may have a looser initial tolerance at power-up, but all usb transmissions from the chip will meet the usb spec- ification. 1 = enabled. the internal clock accuracy is 6 mhz 1.5% after usb traffic is received . 0 = disabled. the internal clock accuracy is 6 mhz 5%. bit 1: internal clock output disable the internal clock output disable is used to keep the internal clock from driving out to the xtalout pin. this bit has no effect in the external oscillator mode. 1 = disable internal clock output. xtalout pin will drive high. 0 = enable the internal clock output. the internal clock is driv- en out to the xtalout pin. bit 0: external oscillator enable at power-up, the chip operates fr om the internal clock by de- fault. setting the external oscillator enable bit high disables the internal clock, and halts the part while the external reso- nator/crystal oscillator is started. clearing this bit has no im- mediate effect, although the st ate of this bit is used when waking out of suspend mode to select between internal and external clock. in in ternal clock mode, xtalin pin will be con- figured as an input with a weak pull-down and can be used as a gpio input (p2.1). 1 = enable the external oscill ator. the clock is switched to external clock mode, as described in section . 0 = enable the internal oscillator. internal/external oscillator operation the internal oscillator provides an operating clock, factory set to a nominal frequency of 6 mhz. this clock requires no external components. at power-up, the chip operates from the internal clock. in this mode, the internal clock is buffered and driven to the xtalout pin by default, and the state of the xtalin pin can be read at port 2.1. while the in ternal clock is enabled, its output can be disabled at the xtalout pin by setting the internal clock output disable bit of the clo ck configuration register. setting the external oscillator enable bit of the clock configu- ration register high disables the internal clock, and halts the part while the external resonator/ crystal oscillator is started. the steps involved in switching from internal to external clock mode are as follows: 1. at reset, chip begins operation using the internal clock. 2. firmware sets bit 0 of the clock configuration register. for example, mov a, 1h ; set bit 0 high (external oscillator enable bit). bit 7 cleared gives faster start-up iowr f8h ; write to clock configuration register 3. internal clocking is halted, the internal oscillator is disabled, and the external clock oscillator is enabled. 4. after the external clock bec omes stable, chip clocks are re-enabled using the external cl ock signal. (note that the time for the external clock to become stable depends on the external resonating devi ce; see next section.) 5. after an additional delay the cpu is released to run. this delay depends on the state of the ext. clock resume delay bit of the clock configuration register. the time is 128 ? s if the bit is 0, or 4 ms if the bit is 1. 6. once the chip has been set to external oscillator, it can only return to internal clock when waking from suspend mode. clearing bit 0 of the clock conf iguration register will not re-enable internal clock mode until suspend mode is entered. see section for more details on suspend mode operation. if the internal clock is enabled, the xtalin pin can serve as a general purpose input, and its state can be read at port 2, bit 1 (p2.1). refer to figure for the port 2 data re gister. in this mode, there is a weak pull-down at the xtalin pin. this input cannot provide an interrupt source to the cpu. external oscillator the user can connect a low-cost ceramic resonator or an external oscillator to the xtalin/xtalout pins to provide a precise reference frequency for the chip clock, as shown in figure . the external components required are a ceramic resonator or crystal and any associated capacitors. to run from the external resonator, the external oscillator enable bit of the clock configuration register must be set to 1, as explained in the previous section. start-up times for the external oscillator depend on the resonating device. ceramic resonator based oscillators typically start in less than 100 ? s, while crystal based oscillators take longer, typically 1 to 10 ms. board capacitance should be minimized on the xtalin and xtalout pins by keeping the traces as short as possible. an external 6-mhz clock can be applied to the xtalin pin if the xtalout pin is left open. reset the usb controller supports three types of resets. the effects of the reset are listed below. the reset types are: 1. low-voltage reset (lvr) 2. brown out reset (bor) 3. watchdog reset (wdr) the occurrence of a reset is recorded in the processor status and control register ( figure 33 ). bits 4 (low-voltage or [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 12 of 53 brown-out reset bit) and 6 (watchdog reset bit) are used to record the occurrence of lvr/bor and wdr respectively. the firmware can interrogate these bits to determine the cause of a reset. the microcontroller begins execution from rom address 0x0000 after a lvr, bor, or wdr reset. although this looks like interrupt vector 0, there is an important difference. reset processing does not push the program counter, carry flag, and zero flag onto program stack. attempting to ex ecute either a ret or reti in the reset handler will cause unpredictable execution results. the following events take place on reset. more details on the various resets are given in the following sections. 1. all registers are reset to thei r default states (all bits cleared, except in processor status and control register). 2. gpio and usb pins are set to high-impedance state. 3. the vreg pin is set to high-impedance state. 4. interrupts are disabled. 5. usb operation is disabled and must be enabled by firmware if desired, as explained in section . 6. for a bor or lvr, the external oscillator is disabled and internal clock mode is activated, followed by a time-out period t start for v cc to stabilize. a wdr does not change the clock mode, and there is no delay for v cc stabilization on a wdr. note that the external oscillator enable (bit 0, figure ) will be cleared by a wdr, but it does not take effect until suspend mode is entered. 7. the program stack pointer (psp) and data stack pointer (dsp) reset to address 0x00. fi rmware should move the dsp for usb applications, as explained in section . 8. program execution begins at address 0x0000 after the appro- priate time-out period. low-voltage reset (lvr) when v cc is first applied to the chip, the internal oscillator is started and the low-voltage reset is initially enabled by default. at the point where v cc has risen above v lvr (see section for the value of v lvr ), an internal counter starts counting for a period of t start (see section for the value of t start ). during this t start time, the microcontroller enters a partial suspend state to wait for v cc to stabilize before it begins executing code from address 0x0000. as long as the lvr circuit is enabled, this reset sequence repeats whenever the v cc pin voltage drops below v lvr . the lvr can be disabled by firmware by setting the low-voltage reset disable bit in the clock configuration register ( figure ). in addition, the lvr is automatically disabled in suspend mode to save power. if the lvr was enabled before entering suspend mode, it becomes active again once the suspend mode ends. when lvr is disabled during normal operation (i.e., by writing ?0? to the low-voltage reset disable bit in the clock configuration register), the chip may enter an unknown state if v cc drops below v lvr . therefore, lvr should be enabled at all times during normal operation. if lvr is disabled (i.e., by firmware or during suspend mode), a secondary low-voltage monitor, bor, becomes active, as described in the next section. the lvr/bor reset bit of the processor status and control register ( figure 33 ), is set to ?1? if either a lvr or bor has occurred. brown out reset (bor) the brown out reset (bor) circuit is always active and behaves like the por. bor is asserted whenever the v cc voltage to the device is below an internally defined trip voltage of approximately 2.5v. the bor re-enables lvr. that is, once v cc drops and trips bor, the part remains in reset until v cc rises above v lvr . at that point, the t start delay occurs before normal operation resumes, and the microcontroll er starts executing code from address 0x00 after the t start delay. in suspend mode, only the bor detection is active, giving a reset if v cc drops below approximately 2.5v. since the device is suspended and code is not executing, this lower reset voltage is safe for retaining the state of all registers and memory. note that in suspend mode, lvr is disabled as discussed in section . watchdog reset (wdr) the watchdog timer reset (wdr) occurs when the internal watchdog timer rolls over. writing any value to the write-only watchdog reset register at address 0x26 will clear the timer. the timer will roll over and wdr will occur if it is not cleared within t watch (see figure 10 ) of the last clear. bit 6 (watchdog reset bit) of the processor status and control register is set to record this event (see section for more details). a watchdog timer reset typically lasts for 2?4 ms, after which the microcon- troller begins execution at rom address 0x0000. figure 5. watchdog reset (wdr, address 0x26) at least 10.1 ms wdr goes high execution begins at rom address 0x0000 2?4 ms since last write to wdr for 2?4 ms 14.6 ms (at f osc = 6 mhz) wdr t watch = 10.1 to [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 13 of 53 suspend mode the cy7c637xxc parts support a versatile low-power suspend mode. in suspend mode, only an enabled interrupt or a low state on the d?/sdata pin will wake the part. two options are available. for lowest power, all internal circuits can be disabled, so only an external event will resu me operation. alternatively, a low-power internal wake-up timer can be used to trigger the wake-up interrupt. this timer is described in section , and can be used to periodically poll the system to check for changes, such as looking for movement in a mouse, while maintaining a low average power. the cy7c637xxc is placed into a low-power state by setting the suspend bit of the processor status and control register ( figure 33 ). all logic blocks in the device are turned off except the gpio interrupt logic, the d?/sdata pin input receiver, and (optionally) the wake-up timer. the clock oscillators, as well as the free-running and watchdog timers are shut down. only the occurrence of an enabled gpio interrupt, wake-up interrupt, spi slave interrupt, or a low state on the d?/sdata pin will wake the part from suspend (d? low indicates non-idle usb activity). once one of these resuming c onditions occurs, clocks will be restarted and the device returns to full operation after the oscil- lator is stable and the selected delay period expires. this delay period is determined by selection of internal vs. external clock, and by the state of the ext. clock resume delay as explained in section . in suspend mode, any enabled and pending interrupt will wake the part up. the state of the in terrupt enable sense bit (bit 2, figure 33 ) does not have any effect. as a result, any interrupts not intended for waking from suspend should be disabled through the global interrupt enable register and the usb end point interrupt enable register (section ). if a resuming condition exists w hen the suspend bit is set, the part will still go into suspend and then awake after the appro- priate delay time. the run bit in the processor status and control register must be set for the part to resume out of suspend. once the clock is stable and the delay time has expired, the microcontroller will execute the in struction following the i/o write that placed the device into suspend mode before servicing any interrupt requests. to achieve the lowest possible current during suspend mode, all i/o should be held at either v cc or ground . in addition, the gpio bit interrupts ( figure 37 and figure 38 ) should be disabled for any pins that are not being used for a wake-up interrupt. this should be done even if the ma in gpio interrupt enable ( figure ) is off. typical code for entering suspend is shown below: ... ; all gpio set to low-power state (no floating pins, and bit interrupts disabled unless using for wake-up) ... ; enable gpio and/or wake-up timer interrupts if desired for wake-up ... ; select clock mode fo r wake-up (see section ) mov a, 09h ; set suspend and run bits iowr ffh ; write to status and control register ? enter suspend, wait for gpio/wake-up interrupt or usb activity nop ; this executes before any isr ... ; remaining code for exiting suspend routine clocking mode on wake-up from suspend when exiting suspend on a wake-up event, the device can be configured to run in either inte rnal or external clock mode. the mode is selected by the state of the external oscillator enable bit in the clock configuration register ( figure ). using the internal clock saves the external oscillator start-up time and keeps that oscillator off for additional power savings. the external oscillator mode can be activated when desired, similar to operation at power-up. the sequence of events for these modes is as follows: wake in internal clock mode: 1. before entering suspend, clear bit 0 of the clock configuration register. this selects internal clock mode after suspend. 2. enter suspend mode by setting the suspend bit of the processor status and control register. 3. after a wake-up event, the internal clock starts immediately (within 2 ? s). 4. a time-out period of 8 ? s passes, and then firmware execution begins. 5. at some later point, to activate external clock mode, set bit 0 of the clock configuration register. this halts the internal clocks while the external cl ock becomes stable. after an additional time-out (128 ? s or 4 ms, see section ), firmware execution resumes. wake in external clock mode: 1. before entering suspend, the external clock must be selected by setting bit 0 of the clock configuration register. make sure this bit is still set when suspend mode is entered. this selects external clock mode after suspend. 2. enter suspend mode by setting the suspend bit of the processor status and control register. 3. after a wake-up event, the external oscillator is started. the clock is monitored for stability (this takes approximately 50?100 ? s with a ceramic resonator). 4. after an additional time-out period (128 ? s or 4 ms, see section ), firmware execution resumes. wake-up timer the wake-up timer runs whenever the wake-up interrupt is enabled, and is turned off whenever that interrupt is disabled. operation is independent of whether the device is in suspend mode or if the global interrupt bit is enabled. only the wake-up timer interrupt enable bit ( figure ) controls the wake-up timer. once this timer is activated, it will give interrupts after its time-out period (see below). these interrupts continue periodically until the interrupt is disabled. whenever the interrupt is disabled, the wake-up timer is reset, so that a subsequent enable always results in a full wake-up time. the wake-up timer can be adjusted by the user through the wake-up timer adjust bits in the clock configuration register ( figure ). these bits clear on reset. in addition to allowing the user to select a range for the wake-up time, a firmware algorithm can be used to tune out initial process and operating condition variations in this wake-up time. this can be done by timing the wake-up interrupt time with the accurate 1.024-ms timer interrupt, and adjusting the timer adjust bits accordingly to approximate the desired wake-up time. [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 14 of 53 general purpose i/o ports ports 0 and 1 provide up to 16 versatile gp io pins that can be read or written (the number of pi ns depends on package type). figure shows a diagram of a gpio port pin. figure 6. block diagram of gpio port (one pin shown) port 0 is an 8-bit port; port 1 cont ains either 2 bits, p1.1?p1.0 in the cy7c63723c, or all 8 bits, p1.7?p1.0 in the cy7c63743c parts. each bit can also be select ed as an interrupt source for the microcontroller, as explained in section . the data for each gpio pin is accessible through the port data register. writes to the port data register store outgoing data state for the port pins, while reads from the port data register return the actual logic value on the port pins, not the port data register contents. each gpio pin is configured independently. the driving state of each gpio pin is determined by the value written to the pin?s data register and by two associated pin?s mode0 and mode1 bits. the port 0 data register is shown in figure 7 , and the port 1 data register is shown in figure 8 . the mode0 and mode1 bits for the two gpio ports are given in figure 9 through figure 12 . table 2. wake-up ti mer adjust settings adjust bits [2:0] (bits [6:4] in figure ) wakeup time 000 (reset state) 1 * t wake 001 2 * t wake 010 4 * t wake 011 8 * t wake 100 16 * t wake 101 32 * t wake 110 64 * t wake 111 128 * t wake see switching characteristics on page 43 for the value of t wake gpio pin v cc 14 k ? gpio mode data out register internal data bus port read port write interrupt enable interrupt control to interrupt controller q1 q2 q3 to capture timers (p0.0, p0.1) and spi (p0.4?p0.7)) logic interrupt polarity 2 threshold select spi bypass (p0.5?p0.7 only) (=1 if spi inactive, or for non-spi pins) (data reg must be 1 for spi outputs) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 15 of 53 figure 7. port 0 data (address 0x00) bit [7:0]: p0[7:0] 1 = port pin is logic high 0 = port pin is logic low figure 8. port 1 data (address 0x01) bit [7:0]: p1[7:0] 1 = port pin is logic high 0 = port pin is logic low figure 9. gpio port 0 mode0 register (address 0x0a) bit [7:0]: p0[7:0] mode 0 1 = port 0 mode 0 is logic high 0 = port 0 mode 0 is logic low figure 10. gpio port 0 mode1 register (address 0x0b) bit [7:0]: p0[7:0] mode 1 1 = port pin mode 1 is logic high 0 = port pin mode 1 is logic low figure 11. gpio port 1 mode0 register (address 0x0c) bit [7:0]: p1[7:0] mode 0 1 = port pin mode 0 is logic high 0 = port pin mode 0 is logic low figure 12. gpio port 1 mode1 register (address 0x0d) bit [7:0]: p1[7:0] mode 1 1 = port pin mode 1 is logic high 0 = port pin mode 1 is logic low each pin can be independently configured as high-impedance inputs, inputs with internal pull-ups, open drain outputs, or tradi- tional cmos outputs with selectable drive strengths. the driving state of each gpio pin is determined by the value written to the pin?s data register and by its associated mode0 and mode1 bits. table 3 lists the configurat ion states based on these bits. the gpio ports default on reset to all data and mode registers cleared, so the pins are all in a high-impedance state. the available gpio output drive strength are: hi-z mode (mode1 = 0 and mode0 = 0) q1, q2, and q3 ( figure ) are off. the gpio pin is not driven internally. performing a read from the port data register re- turn the actual logic value on the port pins. low sink mode (mode1 = 1, mode0 = 0, and the pin?s data register = 0) q1 and q3 are off. q2 is on. the gpio pin is capable of sinking 2 ma of current. medium sink mode (mode1 = 0, mode0 = 1, and the pin?s data register = 0) q1 and q3 are off. q2 is on. the gpio pin is capable of sinking 8 ma of current. bit # 76543210 bit name p0 read/write r/wr/wr/wr/wr/wr/wr/wr/w reset 00000000 bit # 76543210 bit name p1 notes pins 7:2 only in cy7c63743c pins 1:0 in all parts read/write r/wr/wr/wr/wr/wr/wr/wr/w reset 00000000 bit # 76543210 bit name p0[7:0] mode0 read/write wwwwwwww reset 00000000 bit # 76543210 bit name p0[7:0] mode1 read/write wwwwwwww reset 00000000 bit # 76543210 bit name p1[7:0] mode0 read/write wwwwwwww reset 00000000 bit # 76543210 bit name p1[7:0] mode1 read/write wwwwwwww reset 00000000 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 16 of 53 high sink mode (mode1 = 1, mode0 = 1, and the pin?s data register = 0) q1 and q3 are off. q2 is on. the gpio pin is capable of sinking 50 ma of current. high drive mode (mode1 = 0 or 1, mode0 = 1, and the pin?s data register = 1) q1 and q2 are off. q3 is on. the gpio pin is capable of sourcing 2 ma of current. resistive mode (mode1 = 1, mode0 = 0, and the pin?s data register = 1) q2 and q3 are off. q1 is on. the gpio pin is pulled up with an internal 14-k ?? resistor. note that open drain mode can be achieved by fixing the data and mode1 registers low, and switching the mode0 register. input thresholds are cmos, or ttl as shown in the table (see section for the input threshold voltage in ttl or cmos modes). both input modes include hysteresis to minimize noise sensi- tivity. in suspend mode, if a pin is used for a wake-up interrupt using an external r-c circuit, cm os mode is preferred for lowest power. auxiliary input port port 2 serves as an auxiliary input port as shown in figure . the port 2 inputs all have ttl input thresholds. figure 13. port 2 data register (address 0x02) bit [7:6]: reserved bit [5:4]: d+ (sclk) and d? (sdata) states the state of the d+ and d? pins can be read at port 2 data register. performing a read from the port pins returns their logic values. 1 = port pin is logic high 0 = port pin is logic low bit [3:2]: reserved bit 1: p2.1 (internal clock mode only) in the internal clock mode, the xtalin pin can serve as a general purpose input, and its state can be read at port 2, bit 1 (p2.1). see section for more details. 1 = port pin is logic high 0 = port pin is logic low bit 0: p2.0/vreg pin state in ps/2 mode, the vreg pin can be used as an input and its state can be read at port p2.0. section for more details. 1 = port pin is logic high 0 = port pin is logic low usb serial interf ace engine (sie) the sie allows the microcontroller to communicate with the usb host. the sie simplifies the interface between the microcon- troller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: translate the encoded received data and format the data to be transmitted on the bus. crc checking and generation. flag the microcontroller if errors exist during transmission. address checking. ignore the transactions not addressed to the device. send appropriate ack/nak/stall handshakes. token type identification (setup , in, or out). set the appro- priate token bit once a valid token is received. place valid received data in the appropriate endpoint fifos. send and update the data toggle bit (data1/0). bit stuffing/unstuffing. firmware is required to handle the rest of the usb interface with the following tasks: coordinate enumeration by decoding usb device requests. fill and empty the fifos. suspend/resume coordination. verify and select data toggle values. table 3. ports 0 and 1 output control truth table data register mode1 mode0 output drive strength input threshold 0 00 hi-z cmos 1 hi-z ttl 0 01 medium (8 ma) sink cmos 1 high drive cmos 0 10 low (2 ma) sink cmos 1 resistive cmos 0 11 high (50 ma) sink cmos 1 high drive cmos bit # 7 6 5 4 3 2 1 0 bit name reserved d+ (sclk) state d? (sdata) state reserved p2.1 (internal clock mode only) p2.0 vreg pin state read/ write -- r r -- r r reset 00 0 0 00 0 0 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 17 of 53 usb enumeration a typical usb enumeration sequence is shown below. in this description, ?firmware? refers to embedded firmware in the cy7c637xxc controller. 1. the host computer sends a setup packet followed by a data packet to usb address 0 requesting the device de- scriptor. 2. firmware decodes the request and retrieves its device descriptor from the program memory tables. 3. the host computer performs a control read sequence and firmware responds by sending the device descriptor over the usb bus, via the on-chip fifo. 4. after receiving the descriptor, the host sends a setup packet followed by a data packet to address 0 assigning a new usb address to the device. 5. firmware stores the new address in its usb device address register after the no-data control sequence completes. 6. the host sends a request for the device descriptor using the new usb address. 7. firmware decodes the request and retrieves the device descriptor from program memory tables. 8. the host performs a control read sequence and firmware responds by sending its device descriptor over the usb bus. 9. the host generates control reads from the device to request the configuration and report descriptors. 10.once the device receives a set configuration request, its functions may now be used. 11.firmware should take appropriate action for endpoint 1 and/or 2 transactions, which may occur from this point. usb port status and control usb status and control is r egulated by the usb status and control register as shown in figure 14 . figure 14. usb status and control register (address 0x1f) bit 7: ps/2 pull-up enable this bit is used to enable the internal ps/2 pull-up resistors on the sdata and sclk pins. normally the output high level on these pins is v cc , but note that the output will be clamped to approximately 1 volt above v reg if the vreg enable bit is set, or if the device address is enabled (bit 7 of the usb device address register, figure 15 ). 1 = enable ps/2 pull-up resistors. the sdata and sclk pins are pulled up internally to v cc with two resistors of approxi- mately 5 k ? (see section for the value of r ps2 ). 0 = disable ps/2 pull-up resistors. bit 6: v reg enable a 3.3v voltage regulator is in tegrated on chip to provide a voltage source for a 1.5-k ? pull-up resistor connected to the d? pin as required by the usb specification. note that the vreg output has an internal series resistance of approxi- mately 200 ? , the external pull-up resistor required is approx- imately 1.3-k ? (see figure 19 ). 1 = enable the 3.3v output voltage on the vreg pin. 0 = disable. the vreg pin c an be configured as an input. bit 5: usb-ps/2 interrupt select this bit allows the user to select whether an usb bus reset interrupt or a ps/2 activity interrupt will be generated when the interrupt conditions are detected. 1 = ps/2 interrupt mode. a ps/2 activity interrupt will occur if the sdata pin is continuously low for 128 to 256 ? s. 0 = usb interrupt mode (default state). in this mode, a usb bus reset interrupt will occur if the single ended zero (se0, d? and d+ are low) exists for 128 to 256 ? s. see section for more details. bit 4: reserved. must be written as a ?0?. bit 3: usb bus activity the bus activity bit is a ?sticky? bit that detects any non-idle usb event has occurred on the usb bus. once set to high by the sie to indicate the bus activity, this bit retains its logical high value until firmware clears it. writing a ?0? to this bit clears it; writing a ?1? preserves its value. the user firmware should check and clear this bit periodically to detect any loss of bus activity. firmware can clear the bus activity bit, but only the sie can set it. the 1.024-ms timer interrupt service routine is normally used to check and clear the bus activity bit. 1 = there has been bus activity since the last time this bit was cleared. this bit is set by the sie. 0 = no bus activity since last time this bit was cleared (by firmware). bit [2:0]: d+/d? forcing bit [2:0] forcing bits allow firmware to directly drive the d+ and d? pins, as shown in table 4 . outputs are driven with controlled edge rates in these modes for low emi. for forcing the d+ and d? pins in usb mode, d+/d? forcing bit 2 should be 0. set- ting d+/d? forcing bit 2 to ?1? puts both pins in an open-drain mode, preferred for applications such as ps/2 or led driving. bit # 76 5 4 3 2:0 bit name ps/2 pull-up enable vreg enable usb reset- ps/2 activity interrupt mode reserved usb bus activity d+/d? forcing bit read/ write r/w r/w r/w - r/w r/w reset 00 0 0 0000 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 18 of 53 usb device the cy7c637xxc supports one usb device address with three endpoints: ep0, ep1, and ep2. usb address register the usb device address register contains a 7-bit usb address and one bit to enable usb communication. this register is cleared during a reset, setting the usb device address to zero and marking this address as disabled. figure 15 shows the format of the usb address register. in either usb or ps/2 mode, this register is cleared by both hard- ware resets and the usb bus reset. see section for more infor- mation on the usb bus reset ? ps/2 interrupt. bit 7: device address enable this bit must be enabled by firmware before the serial inter- face engine (sie) will respond to usb traffic at the address specified in bit [6:0]. 1 = enable usb device address. 0 = disable usb device address. bit [6:0]: device ad dress bit [6:0] these bits must be set by firmware during the usb enumer- ation process (i.e., setaddress) to the non-zero address as- signed by the usb host. usb control endpoint all usb devices are required to have an endpoint number 0 (ep0) that is used to initialize and control the usb device. ep0 provides access to the device configuration information and allows generic usb status and control accesses. ep0 is bidirec- tional as the device can both receive and transmit data. ep0 uses an 8-byte fifo at sram locations 0xf8-0xff, as shown in section . the ep0 endpoint mode register uses the format shown in figure 16 . the sie provides a locking feat ure to prevent firmware from overwriting bits in the usb endpoint 0 mode register. writes to the register have no effect from the point that bit[6:0] of the register are updated (by the si e) until the firmware reads this register. the cpu can unlock this register by reading it. because of these hardware-locking features, firmware should perform an read after a write to the usb endpoint 0 mode register and usb endpoint 0 count register ( figure 18 ) to verify that the contents have changed as desired, and that the sie has not updated these values. bit [7:4] of this register are cleared by any non-locked write to this register, regardless of the value written. bit 7: setup received 1 = a valid setup packet has been received. this bit is forced high from the start of the data packet phase of the setup transaction until the start of the ack packet returned by the sie. the cpu is prevented from clearing this bit during this interval. while this bit is set to ?1?, the cpu cannot write to the ep0 fifo. this prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data. 0 = no setup received. this bit is cleared by any non-locked writes to the register. bit 6: in received 1 = a valid in packet has been received. this bit is updated to ?1? after the last received packet in an in transaction. this bit is cleared by any non-locked writes to the register. 0 = no in received. this bit is cleared by any non-locked writes to the register. table 4. control modes to force d+/d? outputs d+/d? forcing bit [2:0] control action appli- cation 000 not forcing (sie controls driver) any mode 001 force k (d+ high, d? low) usb mode 010 force j (d+ low, d? high) 011 force se0 (d? low, d+ low) 100 force d? low, d+ low ps/2 mode [2] 101 force d? low, d+ hiz 110 force d? hiz, d+ low 111 force d? hiz, d+ hiz bit # 7 6543210 bit name device address enable device address read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0000000 figure 15. usb device address register (address 0x10) note 2. for ps/2 operation, the d+/d? forcing bit [2:0] = 111b mode must be set initially (one time only) before using the other ps/2 force modes bit # 765 4 3:0 bit name setup received in received out received acked transaction mode bit read/ write r/w r/w r/w r/w r/w reset 000 00000 figure 16. endpoint 0 mode register (address 0x12) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 19 of 53 bit 5: out received 1 = a valid out packet has been received. this bit is updated to ?1? after the last received packet in an out transaction. this bit is cleared by any non-locked writes to the register. 0 = no out received. this bit is cleared by any non-locked writes to the register. bit 4: acked transaction the acked transaction bit is set whenever the sie engages in a transaction to the register's endpoint that completes with an ack packet. 1 = the transaction completes with an ack. 0 = the transaction does not complete with an ack. bit [3:0]: mode bit[3:0] the endpoint modes determine how the sie responds to usb traffic that the host sends to th e endpoint. for example, if the endpoint mode bits [3:0] are set to 0001 which is nak in/out mode as shown in ta ble 8 , the sie will send nak handshakes in response to any in or out token sent to this endpoint. in this nak in/out mode, the sie will send an ack handshake when the host sends a setup token to this endpoint. the mode encoding is shown in ta ble 8 . additional information on the mode bits can be found in ta ble 9 and table 10 . these modes give the firmware total control on how to respond to different tokens sent to the endpoints from the host. in addition, the mode bits are automatically changed by the sie in response to many usb transactions. for example, if the mode bit [3:0] are set to 1011 which is ack out-nak in mode as shown in table 8 , the sie will change the endpoint mode bit [3:0] to nak in/out (0001) mode after issuing an ack handshake in response to an out token. firmware needs to update the mode for the sie to respond appropriate- ly. usb non-control endpoints the cy7c637xxc feature two non- control endpoints, endpoint 1 (ep1) and endpoint 2 (ep2). the ep1 and ep2 mode registers do not have the locking mechanism of the ep0 mode register. the ep1 and ep2 mode registers use the format shown in figure . ep1 uses an 8-byte fifo at sram locations 0xf0?0xf7, ep2 uses an 8-byte fifo at sram locations 0xe8?0xef as shown in section . figure 17. usb endpoint ep1, ep2 mode registers (ad- dresses 0x14 and 0x16) bit 7: stall 1 = the sie will stall an out packet if the mode bits are set to ack-out, and the sie will stall an in packet if the mode bits are set to ack-in. see section for the available modes. 0 = this bit must be set to low for all other modes. bit [6:5]: reserved. must be written to zero during register writes. bit 4: acked transaction the acked transaction bit is set whenever the sie engages in a transaction to the register's endpoint that completes with an ack packet. 1 = the transaction completes with an ack. 0 = the transaction does not complete with an ack. bit [3:0]: mode bit [3:0] the ep1 and ep2 mode bits operate in the same manner as the ep0 mode bits (see section ). usb endpoint counter registers there are three endpoint count er registers, with identical formats for both control and non-control endpoints. these registers contain byte count information for usb transactions, as well as bits for data packet status. the format of these registers is shown in figure 18 . figure 18. endpoint 0,1,2 counter registers (addresses 0x11, 0x13 and 0x15) bit 7: data toggle this bit selects the data packet' s toggle state. for in trans- actions, firmware must set this bi t to the select the transmitted data toggle. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. 1 = data1 0 = data0 bit 6: data valid this bit is used for out and setup tokens only. this bit is cleared to ?0? if crc, bitstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings. refer to table 10 for more details. 1 = data is valid. 0 = data is invalid. if enabled, the endpoint interrupt will occur even if invalid data is received. bit # 7 65 4 3210 bit name stall reserved acked transaction mode bit read/ write r/w - - r/c r/w r/w r/w r/w reset 0 00 0 0000 bit # 7 6 5 4 3210 bit name data to g g l e data valid reserved byte count read/writ e r/w r/w - - r/ w r/ w r/ w r/ w reset 0 0 0 0 0000 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 20 of 53 bit [5:4]: reserved bit [3:0]: byte count bit [3:0] byte count bits indicate the number of data bytes in a trans- action: for in transactions, firmware loads the count with the number of bytes to be transmitted to the host from the end- point fifo. valid values are 0 to 8 inclusive. for out or set- up transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2 to 10 inclusive. for endpoint 0 count register, whenever the count updates from a setup or out transaction, the count register locks and cannot be written by the cpu. reading the register un- locks it. this prevents firmware from overwriting a status up- date on incoming setup or out transactions before firm- ware has a chance to read the data. usb regulator output the vreg pin provides a regulated output for connecting the pull-up resistor required for usb operation. for usb, a 1.5-k ? resistor is connected between the d? pin and the v reg voltage, to indicate low-speed usb operation. since the vreg output has an internal series resistance of approximately 200 ? , the external pull-up resistor required is r pu (see section ). the regulator output is placed in a high-impedance state at reset, and must be enabled by firmware by setting the vreg enable bit in the usb status and control register ( figure 14 ). this simplifies the design of a combination ps/2-usb device, since the usb pull-up resistor can be left in place during ps/2 operation without loading the ps/ 2 line. in this mode, the v reg pin can be used as an input and its state can be read at port p2.0. refer to figure for the port 2 data register. this input has a ttl threshold. in suspend mode, the regulator is automatically disabled. if vreg enable bit is set ( figure 14 ), the vreg pin is pulled up to v cc with an internal 6.2-k ? resistor. this holds the proper v oh state in suspend mode note that enabling the device for usb (by setting the device address enable bit, figure 15 ) activates the internal regulator, even if the vreg enable bit is cleared to 0. this insures proper usb signaling in the case where the vreg pin is used as an input, and an external regulator is provided for the usb pull-up resistor. this also limits the swing on the d? and d+ pins to about 1v above the internal regulator voltage, so the device address enable bit normally should only be set for usb operating modes. the regulator output is only designed to provide current for the usb pull-up resistor. in addition, the output voltage at the vreg pin is effectively disconnected when the cy7c637xxc device transmits usb from the internal sie. this means that the vreg pin does not provide a stable voltage during transmits, although this does not affect usb signaling. ps/2 operation the cy7c637xxc parts are optimized for combination usb or ps/2 devices, through the following features: 1. usb d+ and d? lines can also be used for ps/2 sclk and sdata pins, respectively. with usb disabled, these lines can be placed in a high-impedance state that will pull up to v cc . (disable usb by clearing the address enable bit of the usb device address register, figure 15 ). 2. an interrupt is provided to indicate a long low state on the sdata pin. this eliminates the need to poll this pin to check for ps/2 activity. refer to section for more details. 3. internal ps/2 pull-up resistors can be enabled on the sclk and sdata lines, so no gpio pins are required for this task (bit 7, usb status and control register, figure 14 ). 4. the controlled slew rate outputs from these pins apply to both usb and ps/2 modes to minimize emi. 5. the state of the sclk and sdata pins can be read, and can be individually driven low in an open drain mode. the pins are read at bits [5:4] of port 2, and are driven with the control bits [2:0] of the usb status and control register. 6. the v reg pin can be placed into a high-impedance state, so that a usb pull-up resistor on the d?/sdata pin will not interfere with ps/2 operation (bit 6, usb status and control register). the ps/2 on-chip support circuitry is illustrated in figure 19 . [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 21 of 53 figure 19. diagram of us b-ps/2 system connections d?/sdata d+/sclk 5 k ? 3.3v regulator 5 k ? v cc usb - ps/2 driver 1.3 k ? vreg vreg enable ps/2 pull-up enable port 2.0 on-chip off-chip port 2.5 port 2.4 200 ? [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 22 of 53 serial peripheral interface (spi) spi is a four-wire, full-duplex serial communication interface between a master device and one or more slave devices. the cy7c637xxc spi circuit supports byte serial transfers in either master or slave modes. the block diagram of the spi circuit is shown in figure 20 . the block contains buffers for both transmit and receive data for maximum flexibility and throughput. the cy7c637xxc can be configured as either an spi master or slave. the external interface co nsists of master-out/slave-in (mosi), master-in/sl ave-out (miso), serial clock (sck), and slave select (ss ). spi modes are activated by setti ng the appropriate bits in the spi control register, as described below. figure 20. spi block diagram the spi data register below serves as a transmit and receive buffer. bit [7:0]: data i/o[7:0] writes to the spi data register load the transmit buffer, while reads from this register read the receive buffer contents. 1 = logic high 0 = logic low operation as an spi master only an spi master can initiate a byte/data transfer. this is done by the master writing to the spi data register. the master shifts out 8 bits of data (msb first) along with the serial clock sck for the slave. the master?s outgoi ng byte is replaced with an incoming one from a slave device. when the last bit is received, the shift register contents are transferred to the receive buffer and an interrupt is generated. the receive data must be read from the spi data register before the next byte of data is trans- ferred to the receive buffer, or the data will be lost. when operating as a master, an active low slave select (ss ) must be generated to enable a slave for a byte transfer. this slave select is generated under firmware control, and is not part of the spi internal hardware. any available gpio can be used for the master?s slave select output. when the master writes to the spi data register, the data is loaded into the transmit buffer. if the shift register is not busy shifting a previous byte, the tx buffer contents will be automati- cally transferred into the shift register and shifting will begin. if the shift register is busy, the new byte will be loaded into the shift register only after the active by te has finished and is transferred to the receive buffer. the new byte will then be shifted out. the transmit buffer full (tbf) bit will be set high until the transmit buffer?s data-byte is transferred to the shift register. writing to the transmit buffer while the tbf bit is high will overwrite the old byte in the transmit buffer. the byte shifting and sck generation are handled by the hardware (based on firmware selection of the clock source). data is shifted out on the mosi pin (p0.5) and the serial clock is output on the sck pin (p0.7). da ta is received from the slave on the miso pin (p0.6). the output pins must be set to the desired drive strength, and the gpio data register must be set to 1 to enable a bypass mode for these pins. the miso pin must be configured in the desired gpio input mode. see section for gpio configuration details. 8 bit shift register data bus data bus mosi miso sck ss master / slave control write read 4 tx buffer rx buffer internal sck bit # 76543210 bit name data i/o read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 figure 21. spi data register (address 0x60) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 23 of 53 master sck selection the master?s sck is programmable to one of four clock settings, as shown in figure 20 . the frequency is selected with the clock select bits of the spi control r egister. the hardware provides 8 output clocks on the sck pin (p0.7) for each byte transfer. clock phase and polarity are selected by the cpha and cpol control bits (see figure 20 and 23 ). the master sck duty cycle is nominally 33% in the fastest (2 mbps) mode, and 50% in all other modes. operation as an spi slave in slave mode, the chip receives sck from an external master on pin p0.7. data from the master is shifted in on the mosi pin (p0.5), while data is being shif ted out of the slave on the miso pin (p0.6). in addition, the active low slave select must be asserted to enable the slave for transmit. the slave select pin is p0.4. these pins must be configured in appropriate gpio modes, with the gpio data register set to 1 to enable bypass mode selected for the miso pin. in slave mode, writes to the spi data register load the transmit buffer. if the slave select is asserted (ss low) and the shift register is not busy shifting a previous byte, the transmit buffer contents will be automatically transferred into the shift register. if the shift register is busy, the new byte will be loaded into the shift register only after the active byte has finished and is transferred to the receive buffer. the new byte is then ready to be shifted out (shifting waits for sck from the mast er). if the slave select is not active when the transmit buffer is loaded, data is not transferred to the shift register until slave select is asserted. the transmit buffer full (tbf) bit will be set to ?1? until the transmit buffer?s data-byte is transferred to the shift register. writing to the transmit buffer while the tbf bit is high will overwrite the old byte in the transmit buffer. if the slave select is deasserted before a byte transfer is complete, the transfer is aborted and no interrupt is generated. whenever slave select is asserted, the transmit buffer is automatically reloaded into the shift register. clock phase and polarity must be selected to match the spi master, using the cpha and cpol control bits (see figure 22 and figure 23 ). the spi slave logic continues to operate in suspend, so if the spi interrupt is enabled, the device can go into suspend during a spi slave transaction, and it will wake up at the interrupt that signals the end of the byte transfer. spi status and control the spi control register is shown in figure 22 . the timing diagram in figure 23 shows the clock and data states for the various spi modes. figure 22. spi control register (address 0x61) bit 7: tcmp 1 = tcmp is set to 1 by the hardware when 8-bit transfer is complete. the spi interrupt is asserted at the same time tcmp is set to 1. 0 = this bit is only cleared by firmware. bit 6: tbf transmit buffer full bit. 1 = indicates data in the transmit buffer has not transferred to the shift register. 0 = indicates data in the transmit buffer has transferred to the shift register. bit [5:4] comm mode[1:0] 00 = all communications functions disabled (default). 01 = spi master mode. 10 = spi slave mode. 11 = reserved. bit 3: cpol spi clock polarity bit. 1 = sck idles high. 0 = sck idles low. bit 2: cpha spi clock phase bit (see figure 23 ) bit [1:0]: sck select master mode sck frequency selection (no effect in slave mode): 00 = 2 mbit/s 01 = 1 mbit/s 10 = 0.5 mbit/s 11 = 0.0625 mbit/s bit # 76543 210 bit name tcmp tbf comm mode[1:0] cpol cpha sck select read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000 000 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 24 of 53 figure 23. spi data timing spi interrupt for spi, an interrupt request is gen erated after a byte is received or transmitted. see section for details on the spi interrupt. spi modes for gpio pins the gpio pins used for spi out puts (p0.5?p0.7) contain a bypass mode, as shown in the gpio block diagram ( figure ). whenever the spi block is inac tive (mode[5:4] = 00), the bypass value is 1, which enables normal gpio operation. when spi master or slave modes are acti vated, the appropriate bypass signals are driven by the hardware for outputs, and are held at 1 for inputs. note that the corresponding data bits in the port 0 data register must be set to 1 for each pin being used for an spi output. in addition, the gpio modes are not affected by operation of the spi block, so each pin must be programmed by firmware to the desired drive strength mode. for gpio pins that are not used for spi outputs, the spi bypass value in figure is always 1, for normal gpio operation. msb lsb x ss sck (cpol = 1) sck (cpol = 0) mosi/miso msb lsb x mosi/miso data capture strobe data capture strobe interrupt issued interrupt issued cpha = 1: cpha = 0: table 5. spi pin assignments spi function gpio pin comment slave select (ss ) p0.4 for master mode, firmware sets ss , may use any gpio pin. for slave mode, ss is an active low input. master out, slave in (mosi) p0.5 data ou tput for master, data input for slave. master in, slave out (miso) p0.6 data in put for master, data output for slave. sck p0.7 spi clock: output for master, input for slave. [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 25 of 53 12-bit free-running timer the 12-bit timer operates with a 1- ? s tick, provides two interrupts (128- ? s and 1.024-ms) and allows the firmware to directly time events that are up to 4 ms in duration. the lower eight bits of the timer can be read directly by the firmware. reading the lower eight bits latches the upper four bits into a temporary register. when the firmware reads the upper four bits of the timer, it is actually reading the count stored in the temporary register. the effect of this is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time. figure 24. timer lsb register (address 0x24) bit [7:0]: timer lower eight bits figure 25. timer msb register (address 0x25) bit [7:4]: reserved bit [3:0]: timer upper four bits figure 26. timer block diagram bit # 76543210 bit name timer [7:0] read/write rrrrrrrr reset 00000000 bit # 76543210 bit name reserved timer [11:8] read/write ----rrrr reset 00000000 10 9 7 8 5 6432 1 mhz clock 1.024-ms interrupt 128- ? s interrupt to timer registers 8 1 0 11 l1 l0 l2 l3 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 26 of 53 timer capture registers four 8-bit capture timer register s provide both rising- and falling-edge event timing capture on two pins. capture timer a is c onnected to pin 0.0, and capture timer b is connected to pin 0.1. these can be used to mark th e time at which a rising or falling event occurs at the two gpio pins. each timer will capture eight bits of the free-running timer into its capture timer data register if a ri sing or falling edge event that matches the specif ied rising or falling edge condition at the pin. a prescaler allows selection of the capture timer tick size. interrupts can be individually enabled for the four capture registers. a block diagram is shown in figure . figure 27. capture timers block diagram free-running timer gpio p0.0 11 10 9 8 7 4 3 2 1 0 1 mhz clock rising edge detect falling edge detect timer a rising edge time 6 5 timer a falling edge time prescaler gpio p0.1 rising edge detect falling edge detect timer b rising edge time timer b falling edge time 8-bit capture registers capture timer a interrupt request capture timer b interrupt request capture b falling int enable capture b rising int enable capture a falling int enable capture a rising int enable bit 0, reg 0x44 bit 1, reg 0x44 bit 2, reg 0x44 bit 3, reg 0x44 first edge hold bit 7, reg 0x44 mux [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 27 of 53 the four capture timer data registers are read-only, and are shown in figure through figure 30 . out of the 12-bit free running timer, the 8-bit captured in the capture timer data registers are determined by the prescale bit [2:0] in the capture time r configuration register ( figure 32 ). capture timer a-rising, data register (address 0x40.) figure 28. capture timer a-falling, data register (address 0x41) figure 29. capture timer b-rising, data register (address 0x42) figure 30. capture timer b-falling, data register (address 0x43) figure 31. capture timer status register (address 0x45) bit [7:4]: reserved. bit [3:0]: capture a/b, falling/rising event these bits record the occurrence of any rising or falling edges on the capture gpio pins. bits in this register are cleared by reading the corresponding data register. 1 = a rising or falling event that matches the pin?s rising/falling condition has occurred. 0 = no event that matches the pi n?s rising or falling edge con- dition. because both capture a events (rising and falling) share an interrupt, user?s firmware needs to check the status of both capture a falling and rising event bits to determine what caused the interrupt. this is also true for capture b events. figure 32. capture timer configuration register (address 0x44) bit # 76543210 bit name capture a rising data read/write rrrrrrrr reset 00000000 bit # 76543210 bit name capture a falling data read/write rrrrrrrr reset 00000000 bit # 76543210 bit name capture b rising data read/write rrrrrrrr reset 00000000 bit # 76543210 bit name capture b falling data read/write rrrrrrrr reset 00000000 bit # 7654 3 2 1 0 bit name reserved capture b falling event capture b rising event capture a falling event capture a rising event read/ write ---- r r r r reset 0000 0 0 0 0 bit # 7 654 3 2 1 0 bit name first edge hold prescale bit [2:0] capture b falling int enable capture b rising int enable capture a falling int enable capture a rising int enable read/ write r/w r/w r/w r/w r/w r/w r/w r/w reset 0 000 0 0 0 0 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 28 of 53 bit 7: first edge hold 1 = the time of the first occurrence of an edge is held in the capture timer data register un til the data is read. subse- quent edges are ignored until the capture timer data regis- ter is read. 0 = the time of the most rece nt edge is held in the capture timer data register. that is, if multiple edges have occurred before reading the capture timer, the time for the last one will be read (default state). the first edge hold function applies globally to all four cap- ture timers. bit [6:4]: prescale bit [2:0] three prescaler bits allow the capture timer clock rate to be selected among 5 choices, as shown in table 6 below. bit [3:0]: capture a/b, risi ng/falling interrupt enable each of the four capture timer registers can be individually enabled to provide interrupts. both capture a events share a common interrupt request, as do the two capture b events. in addition to the event enables, the main capture interrupt enables bit in the global interrupt enable register (section ) must be set to activate a capture interrupt. 1 = enable interrupt 0 = disable interrupt table 6. capture timer prescalar settings (step size and range for f clk = 6 mhz) prescale 2:0 captured bits lsb step size range 000 bits 7:0 of free-running timer 1 ?? s 256 ? s 001 bits 8:1 of free-running timer 2 ?? s 512 ? s 010 bits 9:2 of free-running timer 4 ?? s 1.024 ms 011 bits 10:3 of free-running timer 8 ?? s 2.048 ms 100 bits 11:4 of free-running timer 16 ?? s 4.096 ms [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 29 of 53 processor status and control register figure 33. processor status and control register (address 0xff) bit 7: irq pending when an interrupt is generated, it is registered as a pending interrupt. the interrupt will remain pending until its interrupt enable bit is set ( figure and figure ) and interrupts are glo- bally enabled (bit 2, processor status and control register). at that point the internal in terrupt handling sequence will clear the irq pending bit until another interrupt is detected as pending. this bit is only valid if the global interrupt enable bit is disabled. 1 = there are pending interrupts. 0 = no pending interrupts. bit 6: watchdog reset the watchdog timer reset (wdr) occurs when the internal watchdog timer rolls over. the timer will roll over and wdr will occur if it is not cleared within t watch (see section for the value of t watch ). this bit is cleared by an lvr/bor. note that a watchdog reset can occur wit h a por/lvr/bor event, as discussed at the end of this section. 1 = a watchdog reset occurs. 0 = no watchdog reset bit 5: bus interrupt event the bus reset status is set whenever the event for the usb bus reset or ps/2 activity interrupt occurs. the event type (usb or ps/2) is selected by the state of the usb-ps/2 inter- rupt mode bit in the usb status and control register (see figure 14 ). the details on the event conditions that set this bit are given in section . in either mode, this bit is set as soon as the event has lasted for 128?256 ? s, and the bit will be set even if the interrupt is not enabled. the bit is only cleared by firmware or lvr/wdr. 1 = a usb reset occurred or ps/ 2 activity is detected, de- pending on usb-ps/2 interrupt select bit. 0 = no event detected since last cleared by firmware or lvr/wdr. bit 4: lvr/bor reset the low-voltage or brown-out reset is set to ?1? during a power-on reset. firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a lvr/bor condition or a watchdog timeout. this bit is not affected by wdr. note that a lvr/bor event may be fol- lowed by a watchdog reset before firmware begins executing, as explained at the end of this section. 1 = a por or lvr has occurred. 0 = no por nor lvr since this bit last cleared. bit 3: suspend writing a '1' to the suspend bit will halt the processor and cause the microcontroller to enter the suspend mode that sig- nificantly reduces power consum ption. an interrupt or usb bus activity will cause the device to come out of suspend. after coming out of suspend, the device will resume firmware execution at the instruction following the iowr which put the part into suspend. when writing the suspend bit with a resume condition present (such as non-idle usb activity), the sus- pend state will still be entered, followed immediately by the wake-up process (with appropriate delays for the clock start-up). see section for more details on suspend mode operation. 1 = suspend the processor. 0 = not in suspend mode. cleared by the hardware when resuming from suspend. bit 2: interrupt enable sense this bit shows whether interrupts are enabled or disabled. firmware has no direct control over this bit as writing a zero or one to this bit position will have no effect on interrupts. this bit is further gated with the bit settings of the global interrupt enable register ( figure ) and usb endpoint interrupt enable register ( figure ). instructions di, ei, and reti manipulate the state of this bit. 1 = interrupts are enabled. 0 = interrupts are masked off. bit 1: reserved. must be written as a 0. bit 0: run this bit is manipulated by the halt instruction. when halt is executed, the processor clears th e run bit and halts at the end of the current instruction. the processor remains halted until a reset occurs (low-voltage, brown-out, or watchdog). this bit should normally be written as a ?1?. bit # 76543210 bit name irq pending watchdog reset bus interrupt event lvr/bor reset suspend interrupt enable sense reserved run read/write r r/w r/w r/w r/w r - r/w reset 01010001 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 30 of 53 during power-up, or during a low-voltage reset, the processor status and control register is set to 00010001, which indicates a lvr/bor (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). note that during the t start ms partial suspend at start-up (explained in section ), a watchdog reset will also occur. when a wdr occurs during the power-up suspend interval, firmware would read 01010001 from the status and control register after power-up. normally the lvr/bor bit should be cleared so that a subsequent wdr can be clearly identified. note that if a usb bus reset (long se0) is received before firmware examines this register, the bus interrupt event bit would also be set. during a watchdog reset, the processor status and control register is set to 01xx0001, which indicates a watchdog reset (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). interrupts interrupts can be generated by the gpio lines, the internal free-running timer, the spi block, the capture timers, on various usb events, ps/2 activity, or by the wake-up timer. all interrupts are maskable by the global interrupt enable register and the usb end point interrupt enable register. writing a ?1? to a bit position enables the interrupt a ssociated with that bit position. during a reset, the contents of the interrupt enable registers are cleared, along with the global in terrupt enable bit of the cpu, effectively disabling all interrupts. the interrupt controller contains a separate flip-flop for each interrupt. see figure 36 for the logic block diagram of the interrupt controller. when an interru pt is generated it is first regis- tered as a pending interrupt. it will stay pending until it is serviced or a reset occurs. a pending interrupt will only generate an interrupt request if it is enabled by the corresponding bit in the interrupt enable registers. the highest priority interrupt request will be serviced following the completion of the currently executing instruction. when servicing an interrupt, the hardware will first disable all interrupts by clearing the global interrupt enable bit in the cpu (the state of this bit can be read at bit 2 of the processor status and control register). next, the flip-flop of the current interrupt is cleared. this is followed by an automatic call instruction to the rom address associated wit h the interrupt being serviced (i.e., the interrupt vector, see se ction ). the instruction in the interrupt table is typically a jmp instruction to the address of the interrupt service routine (isr). the user can re-enable inter- rupts in the interrupt servic e routine by executing an ei instruction. interrupts can be nest ed to a level limited only by the available stack space. the program counter value as well as the carry and zero flags (cf, zf) are stored onto the program stack by the automatic call instruction generated as pa rt of the interrupt acknowledge process. the user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt. the push a instruction should typically be used as the first command in the isr to save the accumulator value and the pop a instruction should be used ju st before the reti instruction to restore the accumulator value. the program counter, cf and zf are restored and interrupts are enabled when the reti instruction is executed. the di and ei instructions can be used to disable and enable interrupts, respectively. these instructions affect only the global interrupt enable bit of the cpu. if desired, ei can be used to re-enable interrupts while inside an isr, instead of waiting for the reti that exits the is r. while the global interrupt enable bit is cleared, the presence of a pendin g interrupt can be detected by examining the irq sense bit (bit 7 in the processor status and control register). interrupt vectors the interrupt vectors supported by the device are listed in ta b l e 7 . the highest priority interrupt is #1 (usb bus reset / ps/2 activity), and the lowest priority interrupt is #11 (wake-up timer). although reset is not an interrupt, the first instruction executed after a reset is at rom address 0x0000, which corre- sponds to the first entry in the interrupt vector table. interrupt vectors occupy two byte s to allow for a two-byte jmp instruction to the appropriate interr upt service routine (isr). interrupt latency interrupt latency can be calculated from the following equation: interrupt latency = (number of clock cycles remaining in the current instruction) + (10 clock cycles for the call instruction) + (5 clock cycles for the jmp instruction) for example, if a 5 clock cycle in struction such as jc is being executed when an interrupt occurs, the first instruction of the interrupt service routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clo cks (5+10+5) after the interrupt is issued. with a 6-mhz external resonator, internal cpu clock speed is 12 mhz, so 20 clocks take 20/12 mhz = 1.67 ? s. table 7. interrupt vector assignments interrupt vector no. rom address function not applicable 0x0000 execution after reset begins here 1 0x0002 usb bus reset or ps/2 activity interrupt 2 0x0004 128- ? s timer interrupt 3 0x0006 1.024-ms timer interrupt 4 0x0008 usb endpoint 0 interrupt 5 0x000a usb endpoint 1 interrupt 6 0x000c usb endpoint 2 interrupt 7 0x000e spi interrupt 8 0x0010 capture timer a interrupt 9 0x0012 capture timer b interrupt 10 0x0014 gpio interrupt 11 0x0016 wake-up timer interrupt [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 31 of 53 interrupt sources the following sections provide details on t he different types of interrupt sources. figure 34. global interrupt enable register (address 0x20) bit 7: wake-up interrupt enable the internal wake-up timer is normally used to wake the part from suspend mode, but it can also provide an interrupt when the part is awake. the wake-up timer is cleared whenever the wake-up interrupt enable bit is written to a 0, and runs when- ever that bit is written to a 1. when the interrupt is enabled, the wake-up timer provides periodic interrupts at multiples of period, as described in section . 1 = enable wake-up timer for periodic wake-up. 0 = disable and power-off wake-up timer. bit 6: gpio interrupt enable each gpio pin can serve as an interrupt input. during a reset, gpio interrupts are disabled by clearing all gpio interrupt enable registers. writing a ?1? to a gpio interrupt enable bit enables gpio interrupts from the corresponding input pin. these registers are shown in figure 37 for port 0 and figure 38 for port 1. in addition to enabling the desired indi- vidual pins for interrupt, the main gpio interrupt must be en- abled, as explained in section . the polarity that triggers an interrupt is controlled indepen- dently for each gpio pin by the gpio interrup t polarity reg- isters. setting a polarity bit to ?0? allows an interrupt on a falling gpio edge, while setting a polarity bit to ?1? allows an interrupt on a rising gpio edge. the polarity registers reset to 0 and are shown in figure 39 for port 0 and figure for port 1. all of the gpio pins share a single interrupt vector, which means the firmware will need to read the gpio ports with enabled interrupts to determine which pin or pins caused an interrupt.the gpio interrupt st ructure is illustrated in figure . note that if one port pin triggered an interrupt, no other port pins can cause a gpio interrupt until that port pin has re- turned to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. the cy7c637xxc does not assign interrupt priority to different port pins and the port interrupt enable registers are not affected by the interrupt acknowledge process. 1 = enable 0 = disable bit [5:4]: capture timer a and b interrupts there are two capture timer inte rrupts, one for each associated pin. each of these interrupts occurs on an enabled edge of the selected gpio pin(s). for each pin, rising and/or falling edge capture interrupts can be in selected. refer to section . these interrupts are independent of the gpio interrupt, described in the next section. 1 = enable 0 = disable bit 3: spi interrupt enable the spi interrupt occurs at the end of each spi byte transaction, at the final clock edge, as shown in figure 23 . after the interrupt, the received data byte can be read from the spi data register, and the tcmp control bit will be high 1 = enable 0 = disable bit 2: 1.024-ms interrupt enable the 1.024-ms interrupts are periodic timer interrupts from the free-running timer (based on the 6-mhz clock). the user should disable this interrupt before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts (128- ? s interrupt and 1.024-ms interrupt) first or the suspend request first when waking up. 1 = enable. periodic interrupts will be generated approximate- ly every 1.024 ms. 0 = disable. bit 1: 128- ? s interrupt enable the 128- ? s interrupt is another sour ce of timer interrupt from the free-running timer. the user should disable both timer in- terrupts (128- ? s and 1.024-ms) before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first when waking up. 1 = enable. periodic interrupts will be generated approximate- ly every 128 ? s. 0 = disable. bit # 76543210 bit name wake-up interrupt enable gpio interrupt enable capture timer b intr. enable capture timer a intr. enable spi interrupt enable 1.024-ms interrupt enable 128- ? s interrupt enable usb bus reset / ps/2 activity intr. enable read/write r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 32 of 53 bit 0: usb bus reset - ps/2 interrupt enable the function of this interrupt is selectable between detection of either a usb bus reset condition, or ps/2 activity. the se- lection is made with the usb-ps/ 2 interrupt mode bit in the usb status and control register ( figure 14 ). in either case, the interrupt will occur if the selected condition exists for 256 ? s, and may occur as early as 128 ? s. a usb bus reset is indicated by a single ended zero (se0) on the usb d+ and d? pins. the usb bus reset interrupt occurs when the se0 condition ends. ps/2 activity is indicated by a continuous low on the sdata pin. the ps/2 interrupt occurs as soon as the long low state is detected. during the entire interval of a usb bus reset or ps/2 interrupt event, the usb device address register is cleared. the bus reset/ps/2 interrupt may occur 128 ? s after the bus condition is removed. 1 = enable 0 = disable figure 35. endpoint interrupt enable register (address 0x21) bit [7:3]: reserved. bit [2:1]: ep2,1 in terrupt enable there are two non-control endpoint (ep2 and ep1) interrupts. if enabled, a non-control endpo int interrupt is generated when: ? the usb host writes valid data to an endpoint fifo. howev- er, if the endpoint is in ack out modes, an interrupt is gen- erated regardless of data packet validity (i.e., good crc). firmware must check for data validity. ? the device sie sends a nak or stall handshake packet to the usb host during the host attempts to read data from the endpoint (ins). ? the device receives an ack handshake after a successful read transaction (in) from the host. ? the device sie sends a nak or stall handshake packet to the usb host during the host attempts to write data (outs) to the endpoint fifo. 1 = enable 0 = disable refer to table 8 for more information. bit 0: ep0 interrupt enable if enabled, a control endpoint interrupt is generated when: ? the endpoint 0 mode is set to accept a setup token. ? after the sie sends a 0-byte pa cket in the status stage of a control transfer. ? the usb host writes valid data to an endpoint fifo. howev- er, if the endpoint is in ack out modes, an interrupt is gen- erated regardless of what data is received. firmware must check for data validity. ? the device sie sends a nak or stall handshake packet to the usb host during the host attempts to read data from the endpoint (ins). ? the device sie sends a nak or stall handshake packet to the usb host during the host attempts to write data (outs) to the endpoint fifo. 1 = enable ep0 interrupt 0 = disable ep0 interrupt bit # 76543 2 1 0 bit name reserved ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable read/write ----- r/w r/w r/w reset 00000 0 0 0 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 33 of 53 figure 36. interrupt controller logic block diagram bit [7:0]: p0 [7:0] interrupt enable 1 = enables gpio interrupts from the corresponding input pin. 0 = disables gpio interrupts from the corresponding input pin. bit [7:0]: p1 [7:0] interrupt enable 1 = enables gpio interrupts from the corresponding input pin. 0 = disables gpio interrupts from the corresponding input pin. the polarity that triggers an interrupt is controlled independently for each gpio pin by the gpio interrupt polarity registers. figure 39 and figure control the interrupt polarity of each gpio pin. bit [7:0]: p0[7:0] interrupt polarity 1 = rising gpio edge 0 = falling gpio edge clr global interrupt interrupt acknowledge irqout usb-ps/2 clear interrupt interrupt priority encoder enable [0] d q 1 enable bit clr usb-ps/2 irq 128- ? s clr 128- ? s irq 1-ms clr 1-ms irq ep0 irq ep0 clr wake-up irq vector enable [7] clk clr d q clk 1 wake-up clr int wake-up int usb- ep1 irq ep1 clr irq pending irq controlled by di, ei, and reti instructions to cpu cpu ps/2 gpio irq gpio clr ep2 irq ep2 clr capture a irq capture a clr capture b irq capture b clr (reg 0x20) (reg 0x20) clr enable [2] d q 1 clk int ep2 (reg 0x21) int enable sense (bit 7, reg 0xff) (bit 2, reg 0xff) spi irq spi clr bit # 76543210 bit name p0 interrupt enable read/write wwwwwwww reset 00000000 figure 37. port 0 interrupt enable register (address 0x04) bit # 76543210 bit name p1 interrupt enable read/write wwwwwwww reset 00000000 figure 38. port 1 interrupt enable register (address 0x05) bit # 76543210 bit name p0 interrupt polarity read/write wwwwwwww reset 00000000 figure 39. port 0 interrupt polarity register (address 0x06) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 34 of 53 figure 40. port 1 interrupt polarity register (address 0x07) bit [7:0]: p1[7:0] interrupt polarity 1 = rising gpio edge 0 = falling gpio edge figure 41. gpio interrupt diagram bit # 76543210 bit name p1 interrupt polarity read/write wwwwwwww reset 00000000 port bit interrupt or gate gpio interrupt flip flop clr gpio pin 1 = enable 0 = disable port bit interrupt enable register 1 = enable 0 = disable interrupt priority encoder irqout interrupt vector d q m u x 1 (1 input per gpio pin) global gpio interrupt enable (bit 6, register 0x20) ira polarity register [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 35 of 53 usb mode tables the following tables give details on mode setting for the usb serial interface engine (sie) for bot h the control endpoint (ep0) and non-control endpoints (ep1 and ep2). note 3. stall bit is the bit 7 of the usb non-control device endpoint mode registers. refer to section for more explanation. mode column: the 'mode' column contains the mnemonic names given to the modes of the endpoint. the mode of the endpoint is determined by the four-bit binaries in the 'encoding' column as discussed below. the status in and status out modes represent the status in or out stage of the control transfer. encoding column: the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( figure 16 and figure ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0 ] of the endpoint 0 mode register ( figure 16 ) are set to '0001', which is nak in/out mode as shown in table 8 above, the sie of the part will send an ack handshake in response to setup tokens and nak any in or out tokens. for more information on the functionality of the serial interface engine (sie), see section . setup, in, and out columns: depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the device sie's responses when the endpoint receives setup, in, and out tokens respectively. a 'check' in the out column means that upon receiving an out token the sie checks to see whet her the out is of zero length and has a data toggle (data1/0) of 1. if these conditions are true, the sie responds with an ack. if any of the above conditions is not met, the sie will respond with either a stall or ignore. ta b l e 1 0 gives a detailed analysis of all possible cases. a 'tx count' entry in the in column means that the sie will transmit the number of bytes specif ied in the byte count bit [3:0] of the endpoint count register ( figure 18 ) in response to any in token. a 'tx 0 byte' entry in the in column means that the sie will transmit a zero byte packet in response to any in sent to the endpoint. sending a 0 byte packet is to complete the status stage of a control transfer. an 'ignore' means that the device sends no handshake tokens. an 'accept' means that the sie will respond with an ack to a valid setup transaction. comments column: some mode bits are automat ically changed by the sie in response to many usb transacti ons. for example, if the mode bits [3:0] are set to '1111' which is ack in-status out mode as shown in table 8 , the sie will change the endpoint mode bits table 8. usb register mode encoding for control and non-control endpoints mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint nak in/out 0001 accept nak nak on control endpoint, after successfully sending an ack handshake to a setup packet, the sie forces the endpoint mode (from modes other than 0000) to 0001. the mode is also changed by the sie to 0001 from mode 1011 on issuance of ack handshake to an out. status out only 0010 accept stall check for control endpoints stall in/out 0011 accept stall stall for control endpoints ignore in/out 0100 accept ignore ignore for control endpoints reserved 0101 ignore ignore always reserved status in only 0110 accept tx 0 byte stall for control endpoints reserved 0111 ignore tx count ignore reserved nak out 1000 ignore ignore nak in mode 1001, after sending an ack handshake to an out, the sie changes the mode to 1000 ack out( stall [3] =0) ack out (stall [3] =1) 1001 1001 ignore ignore ignore ignore ack stall this mode is changed by the sie to mode 1000 on issuance of ack handshake to an out nak out - status in 1010 accept tx 0 byte nak ack out - nak in 1011 accept nak ack this mode is changed by the sie to mode 0001 on issuance of ack handshake to an out nak in 1100 ignore nak ignore an ack from mode 1101 changes the mode to 1100 ack in (stall [3] =0) ack in( stall [3] =1) 1101 1101 ignore ignore tx count stall ignore ignore this mode is changed by the sie to mode 1100 on issuance of ack handshake to an in nak in - status out 1110 accept nak check an ack from mode 1111 ch anges the mode to 1110 ack in - status out 1111 accept tx count check this mode is changed by the sie to mode 1110 on issuance of ack handshake to an in [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 36 of 53 [3:0] to nak in-status out mode (1110) after acking a valid status stage out token. the fi rmware needs to update the mode for the sie to respond appropriately. see ta b l e 8 for more details on what modes will be changed by the sie. any setup packet to an enabled endpoint with mode set to accept setups will be changed by the sie to 0001 (naking). any mode set to accept a setup will send an ack handshake to a valid setup token. a disabled endpoint will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). firmware normally enables the endpoint mode after a setcon- figuration request. the control endpoint has three status bits for identifying the token type received (setup, in, or out), but the endpoint must be placed in the correct mode to function as such. non-control endpoints should not be placed into modes that accept setups. table 9. decode table for table 10 : ?details of modes for di ffering traffic conditions? endpoint mode encoding properties of incoming packet changes to the internal register made by the sie as a result of the incoming token interrupt? end point mode 3 210 to- ken count buffer dval dtog dval count setup in out ack 3 2 1 0 re- sponse int bit[3:0], figure 18 sie?s re- sponse data valid (bit 6, figure 18 ) endpoint mode changed by the sie. data 0/1 (bit 7, figure 18 ) received token (setup, in,out) the validity of the received data acknowledge transaction completed (bit4, figure 16 /3) the quality status of the dma buffer pid status bits (bit[7:5], figure 16 ) the number of received bytes legend: uc: unchanged tx: transmit tx0: transmit 0-length packet x: don?t care rx: receive available for control endpoint only [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 37 of 53 the response of the sie can be summarized as follows: 1. the sie will only respond to valid transactions, and will ignore non-valid ones. 2. the sie will generate an interrupt when a valid transaction is completed or when the fifo is corrupted. fifo corruption occurs during an out or setup transaction to a valid internal address, that ends with a non-valid crc. 3. an incoming data packet is valid if the count is < endpoint size + 2 (includes crc) and passes all error checking; 4. an in will be ignored by an out configured endpoint and visa versa. 5. the in and out pid status is updated at the end of a trans- action. 6. the setup pid status is updated at the beginning of the data packet phase. 7. the entire endpoint 0 mode register and the count register are locked to cpu writes at the end of any transaction to that endpoint in which an ack is transferred. these registers are only unlocked by a cpu read of these registers, and only if that read happens after the transaction completes. this repre- sents about a 1- ? s window in which the cpu is locked from register writes to these usb r egisters. normally the firmware should perform a register read at the beginning of the endpoint isrs to unlock and get the mode register infor- mation. the interlock on the mode and count registers ensures that the firmware reco gnizes the changes that the sie might have made during the previous transaction. table 10. details of modes fo r differing tra ffic conditions end point mode pid set end point mode 3210 rcved token cou nt buffer dval dtog dval coun t set- up in ou t ack 3 2 1 0 response int setup packet (if accepting) see8 setup <= 10 data valid up- dates 1 up- dates 1 u c uc 1 0 001ack ye s see8 setup > 10 junk x up- dates up- dates up- dates 1 u cucuc nochang e ignore ye s see 8 setup x junk invalid up- dates 0 up- dates 1 u cucuc nochang e ignore ye s disabled 0000xxucxucucucuc u cucuc nochang e ignore no nak in/out 0001out x uc x uc uc uc uc u c1 uc nochang enak ye s 0 0 0 1 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 0 0 0 1 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 0 0 0 1 in x uc x uc uc uc uc 1 uc uc nochang enak ye s ignore in/out 0100out x uc x uc uc uc uc u cucuc nochang e ignore no 0 1 0 0 in x uc x uc uc uc uc u cucuc nochang e ignore no stall in/out 0011out x uc x uc uc uc uc u c1 uc nochang estall ye s 0 0 1 1 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 0 0 1 1 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 0 0 1 1 in x uc x uc uc uc uc 1 uc uc nochang estall ye s control write ack out/nak in 1011out <= 10 data valid up- dates 1 up- dates uc u c 1 1 0 001ack ye s 1 0 1 1 out > 10 junk x up- dates up- dates up- dates uc u c1 uc nochang e ignore ye s 1 0 1 1 out x junk invalid up- dates 0 up- dates uc u c1 uc nochang e ignore ye s [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 38 of 53 1 0 1 1 in x uc x uc uc uc uc 1 uc uc nochang enak ye s nak out/status in 1010out <= 10 uc valid uc uc uc uc u c1 uc nochang enak ye s 1 0 1 0 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 1 0 1 0 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 1 0 1 0 in x uc x uc uc uc uc 1 uc 1 nochang etx 0 byte ye s status in only 0110out <= 10 uc valid uc uc uc uc u c 1 uc 0 011stall ye s 0 1 1 0 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 0 1 1 0 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 0 1 1 0 in x uc x uc uc uc uc 1 uc 1 nochang etx 0 byte ye s control read ack in/status out 1 1 1 1 out 2 uc valid 1 1 up- dates uc u c1 1 nochang eack ye s 1 1 1 1 out 2 uc valid 0 1 up- dates uc u c 1 uc 0 011stall ye s 1 1 1 1 out !=2 uc valid up- dates 1 up- dates uc u c 1 uc 0 011stall ye s 1 1 1 1 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 1 1 1 1 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 1 1 1 1 in x uc x uc uc uc uc 1 uc 1 1 1 1 0 ack (back) ye s nak in/status out 1 1 1 0 out 2 uc valid 1 1 up- dates uc u c1 1 nochang eack ye s 1 1 1 0 out 2 uc valid 0 1 up- dates uc u c 1 uc 0 011stall ye s 3 2 1 0 token coun t buffer dval dtog dval coun t set- up in ou t ack 3 2 1 0 response int 1 1 1 0 out !=2 uc valid up- dates 1 up- dates uc u c 1 uc 0 011stall ye s 1 1 1 0 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 1 1 1 0 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 1 1 1 0 in x uc x uc uc uc uc 1 uc uc nochang enak ye s status out only 0 0 1 0 out 2 uc valid 1 1 up- dates uc u c1 1 nochang eack ye s 0 0 1 0 out 2 uc valid 0 1 up- dates uc u c 1 uc 0 011stall ye s 0 0 1 0 out !=2 uc valid up- dates 1 up- dates uc u c 1 uc 0 011stall ye s 0 0 1 0 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 0 0 1 0 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 0 0 1 0 in x uc x uc uc uc uc 1 uc uc 0 0 1 1 stall ye s table 10. details of modes fo r differing tra ffic conditions (continued) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 39 of 53 out endpoint ack out, stall bit = 0 ( figure ) 1001out <= 10 data valid up- dates 1 up- dates uc u c 1 1 1 000ack ye s 1 0 0 1 out > 10 junk x up- dates up- dates up- dates uc u c1 uc nochang e ignore ye s 1 0 0 1 out x junk invalid up- dates 0 up- dates uc u c1 uc nochang e ignore ye s 1 0 0 1 in x uc x uc uc uc uc u cucuc nochang e ignore no ack out, stall bit = 1 ( figure ) 1001out <= 10 uc valid uc uc uc uc u c1 uc nochang estall ye s 1 0 0 1 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 1 0 0 1 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 1 0 0 1 in x uc x uc uc uc uc u cucuc nochang e ignore no nak out 1000out <= 10 uc valid uc uc uc uc u c1 uc nochang enak ye s 1 0 0 0 out > 10 uc x uc uc uc uc u cucuc nochang e ignore no 1 0 0 0 out x uc invalid uc uc uc uc u cucuc nochang e ignore no 1 0 0 0 in x uc x uc uc uc uc u cucuc nochang e ignore no reserved 0101out x up- dates up- dates up- dates up- dates up- dates uc u c1 1 nochang erx ye s 0 1 0 1 in x uc x uc uc uc uc u cucuc nochang e ignore no in endpoint ack in, stall bit = 0 ( figure ) 1101out x uc x uc uc uc uc u cucuc nochang e ignore no 1 1 0 1 in x uc x uc uc uc uc 1 uc 1 1 1 0 0 ack (back) ye s ack in, stall bit = 1 ( figure ) 1101out x uc x uc uc uc uc u cucuc nochang e ignore no 1 1 0 1 in x uc x uc uc uc uc 1 uc uc nochang estall ye s nak in 1100out x uc x uc uc uc uc u cucuc nochang e ignore no 1 1 0 0 in x uc x uc uc uc uc 1 uc uc nochang enak ye s reserved 0111out x uc x uc uc uc uc u cucuc nochang e ignore no 0 1 1 1 in x uc x uc uc uc uc 1 uc uc nochang etx ye s table 10. details of modes fo r differing tra ffic conditions (continued) [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 40 of 53 register summary address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write/ both/ default/ reset gpio configuration ports 0, 1 and 2 0x00 port 0 data p0 bbbbbbbb 00000000 0x01 port 1 data p1 bbbbbbbb 00000000 0x02 port 2 data reserved d+(sclk) state d- (sdata) state reserved p2.1 (int clk mode only vreg pin state -- rr -- rr 00000000 0x0a gpio port 0 mode 0 p0[7:0] mode0 wwwwwwww 00000000 0x0b gpio port 0 mode 1 p0[7:0] mode1 wwwwwwww 00000000 0x0c gpio port 1 mode 0 p1[7:0] mode0 wwwwwwww 00000000 0x0d gpio port 1 mode 1 p1[7:0] mode1 wwwwwwww 00000000 0x04 port 0 interrupt enable p0[7:0] interrupt enable wwwwwwww 00000000 0x05 port 1 interrupt enable p1[7:0] interrupt enable wwwwwwww 00000000 0x06 port 0 interrupt polarity p0[7:0] interrupt polarity wwwwwwww 00000000 0x07 port 1 interrupt polarity p1[7:0] interrupt polarity wwwwwwww 00000000 clock config. 0xf8 clock configuration ext. clock resume delay wake-up timer adjust bit [2:0] low-voltage reset disable precision usb clocking enable internal clock output disable external oscillator enable bbbbbbbb 00000000 endpoint 0, i and 2 configuration 0x10 usb device address device address enable device address bbbbbbbb 00000000 0x12 ep0 mode setup received in received out received acked transaction mode bit bbbbbbbb 00000000 0x14, 0x16 ep1, ep2 mode register stall reserved acked transaction mode bit b -- bbbbb 00000000 0x11, 0x13, and 0x15 ep0,1, and 2 counter data 0/1 to g g l e data valid reserved byte count bb -- bbbb 00000000 usb- sc 0x1f usb status and control ps/2 pull-up enable vreg enable usb reset-ps/2 activity interrupt mode reserved usb bus activity d+/d- forcing bit bbb - bbbb 00000000 interrupt 0x20 global interrupt enable wake-up interrupt enable gpio interrupt enable capture timer b intr. enable capture timer a intr. enable spi interrupt enable 1.024 ms interrupt enable 128 ? s interrupt enable usb bus reset-ps/2 activity intr. enable bbbbbbbb 00000000 0x21 endpoint interrupt enable reserved ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable ----- bbb 00000000 timer 0x24 timer lsb timer bit [7:0] rrrrrrrr 00000000 0x25 timer (msb) reserved timer bit [11:8] ---- rrrr 00000000 spi 0x60 spi data data i/o bbbbbbbb 00000000 0x61 spi control tcmp tbf comm mode [1:0] cpol cpha sck select bbbbbbbb 00000000 capture timer 0x40 capture timer a-rising, data register capture a rising data rrrrrrrr 00000000 0x41 capture timer a-falling, data register capture a falling data rrrrrrrr 00000000 0x42 capture timer b-rising, data register capture b rising data rrrrrrrr 00000000 0x43 capture timer b-falling, data register capture b falling data rrrrrrrr 00000000 0x44 capture timer configuration first edge hold prescale bit [2:0] capture b falling intr enable capture b rising intr enable capture a falling intr enable capture a rising intr enable bbbbbbbb 00000000 0x45 capture timer status reserved capture b falling event capture b rising event capture a falling event capture a rising event ---- bbbb 00000000 proc sc. 0xff process status & control irq pending watch dog reset bus interrupt event lvr/bor reset suspend interrupt enable sense reserved run rbbbbr - b see section [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 41 of 53 absolute maximum ratings storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied...... ?0c to +70c supply voltage on v cc relative to v ss ..........?0.5v to +7.0v dc input voltage .................................. ?0.5v to +v cc +0.5v dc voltage applied to outputs in high z state ?0.5v to + v cc +0.5v maximum total sink output current into port 0 and 1 and pins70 ma maximum total source output current into port 0 and 1 and pins30 ma maximum on-chip power dissipation on any gpio pin50 mw power dissipation...................... ............................... 300 mw static discharge voltage ........ ........... ........... ............ > 2000v latch-up current ................................................... > 200 ma dc characteristics fosc = 6 mhz; operating temperature = 0 to 70c parameter conditions min. max. unit general v cc1 operating voltage note 4 v lvr 5.5 v v cc2 operating voltage note 4 4.35 5.25 v i cc1 v cc operating supply current ? internal oscillator mode typical i cc1 = 16 ma [5] v cc = 5.5v, no gpio loading v cc = 5.0v. t = room temperature 20 ma i cc2 v cc operating supply current ? external oscillator mode typical i cc2 = 13 ma [5] v cc = 5.5v, no gpio loading v cc = 5.0v. t = room temperature 17 ma i sb1 standby current ? no wake-up osc oscillator off, d? > 2.7v 25 ? a i sb2 standby current ? with wake-up osc oscillator off, d? > 2.7v 75 ? a v pp programming voltage (disabled) ?0.4 0.4 v t rsntr resonator start-up interval v cc = 5.0v, ceramic resonator 256 ? s i il input leakage current any i/o pin 1 ? a i snk max i ss gpio sink current cumulative across all ports [6] 70 ma i src max i cc gpio source current cumulative across all ports [6] 30 ma low-voltage and power-on reset v lvr low-voltage reset trip voltage v cc below v lvr for >100 ns [7] 3.5 4.0 v t vccs v cc power-on slew time linear ramp: 0 to 4v [8] 100 ms usb interface v reg vreg regulator output voltage load = r pu +r pd [9, 10] 3.0 3.6 v c reg capacitance on vreg pin external cap not required 300 pf v ohu static output high, driven r pd to gnd [4] 2.8 3.6 v notes 4. full functionality is guaranteed in v cc1 range, except usb transmitter specifications and gpio output currents are guaranteed for v cc2 range. 5. bench measurements taken under nominal operating co nditions. spec cannot be guaranteed at final test. 6. total current cumulative across all port pins, limited to minimize power and ground-drop noise effects. 7. lvr is automatically disabled during suspend mode. 8. lvr will re-occur whenever v cc drops below v lvr . in suspend or with lvr disabled, bor occurs whenever v cc drops below approximately 2.5v. 9. v reg specified for regulator enabled, idle conditions (i.e., no usb traffic), with load resistors listed. during usb transmits from the internal sie, the vreg output is not regulated, and should not be used as a general source of regulated voltage in that case. during receive of usb data, the vreg output drops when d? is low due to internal series resistance of approximately 200 ? at the vreg pin. 10. in suspend mode, v reg is only valid if r pu is connected from d? to vreg pin, and r pd is connected from d? to ground. [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 42 of 53 note 11. the 200 ? internal resistance at the vreg pin gives a standard usb pull-up using this value. alternately, a 1.5 k ? ,5%pull-up from d? to an external 3.3v supply can be used. v olu static output low with r pu to vreg pin 0.3 v v ohz static output high, idle or suspend r pd connected d? to gnd, r pu connected d? to vreg pin [4] 2.7 3.6 v v di differential input sens itivity |(d+)?(d?)| 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance 20 pf i lo hi-z state data line leakage 0 v < v in <3.3 v (d+ or d? pins) ?10 10 ? a r pu external bus pull-up resistance (d?) 1.3 k ? 2% to v reg [11] 1.274 1.326 k ? r pd external bus pull-down resistance 15 k ?? 5% to gnd 14.25 15.75 k ? ps/2 interface v olp static output low isink = 5 ma, sdata or sclk pins 0.4 v r ps2 internal ps/2 pull-up resistance s data, sclk pins, ps/2 enabled 3 7 k ? general purpose i/o interface r up pull-up resistance 8 24 k ? v icr input threshold voltage, cmos mode low to high edge, port 0 or 1 40% 60% v cc v icf input threshold voltage, cmos mode high to low edge, port 0 or 1 35% 55% v cc v hc input hysteresis voltage, cmos mode hi gh to low edge, port 0 or 1 3% 10% v cc v ittl input threshold voltage, ttl mode ports 0, 1, and 2 0.8 2.0 v v ol1a v ol1b output low voltage, high drive mode i ol1 = 50 ma, ports 0 or 1 [4] i ol1 = 25 ma, ports 0 or 1 [4] 0.8 0.4 v v v ol2 output low voltage, medium drive mode i ol2 = 8 ma, ports 0 or 1 [4] 0.4 v v ol3 output low voltage, low drive mode i ol3 = 2 ma, ports 0 or 1 [4] 0.4 v v oh output high voltage, strong drive mode port 0 or 1, i oh = 2 ma [4] v cc ?2 v r xin pull-down resistance, xtalin pin internal clock mode only 50 k ? dc characteristics fosc = 6 mhz; operating tem perature = 0 to 70c (continued) parameter conditions min. max. unit [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 43 of 53 switching characteristics parameter description conditions min. max. unit internal clock mode f iclk internal clock frequency internal clock mode enabled 5.7 6.3 mhz f iclk2 internal clock frequency, usb mode internal clock mode enabled, bit 2 of register 0xf8h is set (precision usb clocking) [12] 5.91 6.09 mhz external os cillator mode t cyc input clock cycle time usb operation, with external 1.5% ceramic resonator or crystal 164.2 169.2 ns t ch clock high time 0.45 t cyc ns t cl clock low time 0.45 t cyc ns reset timing t start time-out delay after lvr/bor 24 60 ms t wake internal wake-up period enabled wake-up interrupt [13] 15ms t watch watchdog timer period f osc = 6 mhz 10.1 14.6 ms usb driver characteristics t r transition rise time cload = 200 pf (10% to 90% [4] )75 ns t r transition rise time cload = 600 pf (10% to 90% [4] )300ns t f transition fall time cload = 200 pf (10% to 90% [4] )75 ns t f transition fall time cload = 600 pf (10% to 90% [4] )300ns t rfm rise/fall time matching t r /t f [4, 14] 80 125 % v crs output signal crossover voltage [18] cload = 200 to 600 pf [4] 1.3 2.0 v usb data timing t drate low speed data rate ave. bit rate (1.5 mb/s 1.5%) 1.4775 1.5225 mb/s t djr1 receiver data jitter tolerance to next transition [15] ?75 75 ns t djr2 receiver data jitter tolerance for paired transitions [15] ?45 45 ns t deop differential to eop transition skew note 15 ?40 100 ns t eopr2 eop width at receiver accepts as eop [15] 670 ns t eopt source eop width 1.25 1.50 ? s t udj1 differential driver jitter to next transition, figure 46 ?95 95 ns t udj2 differential driver jitter to paired transition, figure 46 ?150 150 ns t lst width of se0 during diff. transition 210 ns non-usb mode driver characteristics note 16 t fps2 sdata/sck transition fall time cload = 150 pf to 600 pf 50 300 ns spi timing see figures 47 to 50 [17] t smck spi master clock rate f clk /3; see figure 20 2mhz t ssck spi slave clock rate 2.2 mhz notes 12. initially f iclk2 = f iclk until a usb packet is received. 13. wake-up time for wake-up adjust bits cleared to 000b (minimum setting) 14. tested at 200 pf. 15. measured at cross-over point of differential data signals. 16. non-usb mode refers to driving the d?/sdata and/or d+/sclk pi ns with the control bits of the usb status and control register , with control bit 2 high. 17. spi timing specified for c apacitive load of 50 pf, with gp io output mode = 01 (medium low drive, strong high drive). 18. per the usb 2.0 specification, table 7.7, note 10, the first transition from the idle state is excluded. [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 44 of 53 figure 42. clock timing t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ns t mdo master data output time sck to data valid ?25 50 ns t mdo1 master data output time, first bit with cpha = 1 time before leading sck edge 100 ns t msu master input data set-up time 50 ns t mhd master input data hold time 50 ns t ssu slave input data set-up time 50 ns t shd slave input data hold time 50 ns t sdo slave data output time sck to data valid 100 ns t sdo1 slave data output time, first bit with cpha = 1 time after ss low to data valid 100 ns t sss slave select set-up time before first sck edge 150 ns t ssh slave select hold time after last sck edge 150 ns figure 43. usb data signal timing switching characteristics (continued) parameter description conditions min. max. unit clock t cyc t cl t ch 90% 10% 90% 10% d ? d ? t r t f v crs v oh v ol [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 45 of 53 figure 44. receiver jitter tolerance figure 45. differential to eop transition skew and eop width figure 46. differential data jitter differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 46 of 53 figure 47. spi master timing, cpha = 0 figure 48. spi slave timing, cpha = 0 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 47 of 53 figure 49. spi master timing, cpha = 1 msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb figure 50. spi sl ave timing, cpha = 1 msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 48 of 53 package diagrams figure 51. 18-pin pdip (300-mil) molded dip ordering information ordering code eprom size package name package type operating range cy7c63723c-pxc 8 kb p3 18-pin (300-mil) lead-free pdip commercial cy7c63723c-sxc 8 kb s3 18-pin small outline lead-free package commercial CY7C63743C-PXC 8 kb p13 24-pin (300-mil) lead-free pdip commercial cy7c63743c-sxc 8 kb s13 24-pin small outline lead-free package commercial cy7c63743c-qxc 8 kb q13 24-lead qsop lead-free package commercial cy7c63722c-xc 8 kb ? 25-pad die form commercial 51-85010 *c [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 49 of 53 figure 52. 18l soic .463 x.300 x .0932 inches figure 53. 24-pin soic (.615 x .300 x .0932 inches 51-85023 *c 51-85025 *e [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 50 of 53 figure 54. 24-pin pdip 1.260 x .270 x .140 i figure 55. 24-pin qsop 8.65 x 3.9 x 1.44 mm 51-85013 *c 51-85055 *c [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 51 of 53 figure 56. die form ta b l e 11 below shows the die pad coordinates for the cy7c63722c-xc. the c enter location of each bond pad is relative to the bottom left corner of the die which has coordinate (0,0). 4 5 6 7 8 9 3 24 23 22 21 20 19 18 11 12 13 14 15 16 17 10 2 1 25 (1907, 3001) (0,0) y x die step: 1907 x 3011 microns die size: 1830.8 x 2909 microns die thickness: 14 mils = 355.6 microns pad size: 80 x 80 microns cypress logo table 11. cy7c63722c-xc probe pad coordinates in microns ((0,0) to bond pad centers) pad number pin name x (microns) y (microns) 1 p0.0 788.95 2843.15 2 p0.1 597.45 2843.15 3 p0.2 406.00 2843.15 4 p0.3 154.95 2687.95 5 p1.0 154.95 2496.45 6 p1.2 154.95 2305.05 7 p1.4 154.95 2113.60 8 p1.6 154.95 1922.05 9 vss 154.95 1730.90 10 vss 154.95 312.50 11 vpp 363.90 184.85 12 vreg 531.70 184.85 13 xtalin 1066.55 184.85 14 xtalout 1210.75 184.85 15 vcc 1449.75 184.85 16 d? 1662.35 184.85 17 d+ 1735.35 289.85 18 p1.7 1752.05 1832.75 19 p1.5 1752.05 2024.30 20 p1.3 1752.05 2215.75 21 p1.1 1752.05 2407.15 22 p0.7 1752.05 2598.65 23 p0.6 1393.25 2843.15 24 p0.5 1171.80 2843.15 25 p0.4 980.35 2843.15 [+] feedback
cy7c63722c cy7c63723c cy7c63743c document #: 38-08022 rev. *e page 52 of 53 document history page document title: cy7c63722c, cy7c63723c, cy7c63743c encore? usb combination low-speed usb and ps/2 peripheral controller document number: 38-08022 rev. ecn no. issue date orig. of change description of change ** 118643 10/22/02 bon converted from spec 38-00944 to spec 38-08022. added notes 17, 18 to section 26 removed obsolete parts (63722-pc and 63742) added die sale added section 23 (register summary) *a 243308 see ecn kku added 24 qsop package added lead-free packages to section 27 reformatted to update format *b 267229 see ecn ari corrected part number in the ordering information section *c 429169 see ecn tyj updated part numbers with ?c? part numbers changed to ?cypress perform? logo added the 24-qsop part offering *d 3057657 10/13/2010 ajha added ?not recommended for new designs? watermark in the pdf. updated package diagrams. updated template. *e 3229083 04/15/2011 nxz sunset review. no technical updates. package diagram updated 51-85025 *e [+] feedback
document #: 38-08022 rev. *e revised april 15, 2011 page 53 of 53 encore is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be th e trademarks of their respective holders. cy7c63722c cy7c63723c cy7c63743c ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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